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2019-07-31mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2Seunghwan Kim
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku. More fine-tuning will happen later. BUG=b:1704071 BRANCH=none TEST=build Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34397 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch/variants/hatch: Set PCH Thermal Threshold value to 77 deg CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=133345634 BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Hatch. Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/kukui: Enable config for coreboot displayYongqiang Niu
BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31521 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/octopus: Override DDI1 DDC SDA/SCL for HDMIWisley Chen
The device Dorp uses the variant Meep, and supports HDMI. -sku33 (HDMI) -sku34 (HDMI + keyboard backlight) -sku35 (HDMI + Touchscreen) -sku36 (HDMI + keyboard backlight + Touchscreen) BUG=b:136522841 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I59ba2e56cf2f83ca9d533454570bcdd39c0a2e7c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34509 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/octopus: Override VBT selection for DorpWisley Chen
For dorp HDMI sku, select VBT which enables HDMI output. -sku33 (HDMI) -sku34 (HDMI + keyboard backlight) -sku35 (HDMI + Touchscreen) -sku36 (HDMI + keyboard backlight + Touchscreen) Cq-Depend: chrome-internal:1502253 BUG=b:136522841 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I62262378f85bb899073ffac7804be876e649e429 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-07-30mb/google/hatch: Enable chipset_lockdown coreboot config for hatchSubrata Banik
This patch enables lockdown configuration for hatch family (hatch, kindred, helios and kohaku) BUG=b:138200201 Change-Id: Ia6dc90156dc76fde490b25cf833da3cf80f664f2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-30mb/google/hatch: Add option to enable WiFi SAR configsFurquan Shaikh
This change adds a user selectable option to enable all WiFi SAR configs that apply to hatch. BUG=b:138177048 Change-Id: I4b72f90896841e7c556d4a1b8cdad8ca89d01021 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-29mb/google/octopus: Add keyboard backlight supportWisley Chen
Dorp device support keyboard backlight, so enable it. BUG=b:138413969 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: If0c7b22b4be2a5d5216404a6944ac887883e9a47 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-07-26mb/google/hatch/helios: Update GPIO and device treeTim Wawrzynczak
Based on updated schematics, change polarity of USI_INT, and add the reset and enable GPIOs to the touchscreen ACPI node. The stop GPIO can't be used with the current implementation of _ON, as the way it's wired will cause power sequencing to fail. BUG=b:137133194, b:138240502 BRANCH=none TEST=Compiles, don't have next board rev to test with Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-25mb/google/poppy/variant/nami: add sku ids of bardRen Kuo
add two sku ids of bard: 0x1009CE0 0x1009CE2 BUG=b:137892804 TEST=emerge-nami coreboot Change-Id: I299ccb36739d83e38f37e0b2cbba44c34343c975 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__Kyösti Mälkki
Use explicit simple PCI config accessors here. Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-23mb/google/octopus/variants/fleex: Remove gpio NC setting for enabling I2C0Frank Wu
Enable I2C0 in fleex then verify EMR function successfully BUG=b:135968368 BRANCH=octopus TEST=EMR function working normally with I2C0 in Grob360S. Change-Id: I784ff32418bc839bcec14fbfd7236f708828690e Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-23mb/google/hatch: Add FP MCU to helios device treePhilip Chen
BUG=b:136606255 Change-Id: I8fa29dc96e7a066f6708ede6b7bee2382c7008cb Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mediatek/mt8183: support more EMCP LPDDR4X DDR bootupHuayang Duan
Support SANDISK SDADA4CR-128G, SAMSUNG KMDP6001DA-B425, KMDV6001DA-B620 EMCP LPDDR4X DDR bootup. BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM Change-Id: I7de4c9a27282d3d00f51adf46dcb3d2f3984bfff Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-21mb/google/kukui: Introduce a new 'Jacuzzi' familyHung-Te Lin
The 'Jacuzzi' is a different base board that will share most of Kukui design. For AP firmware, there will be only a few changes expected, mostly in display (for MIPI bridge) and EC/keyboard so we want to create it as variants inside Kukui folder, not forking a new directory. BUG=b:137517228 TEST=make menuconfig; select 'krane' and build; select 'jacuzzi' and build. Change-Id: Ic2b04e01628dc3db40f79f9bbdd5cc77d9466753 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34344 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/hatch: Remove hatch_whlPhilip Chen
Hatch_whl variant is deprecated. BUG=b:137180390 Change-Id: I88fa201398ad5fb70da48d022f1ae86fecafa660 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34432 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21mainboard/google/kahlee: create treeya variantChris Wang
This is based on the grunt variant. BUG=b:135551210 BRANCH=none TEST=emerge-grunt coreboot chromeos-bootimage Ensure that image-treeya.*.bin are created Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I40f3c9de87350777b02dd91d8c5b9dbe2eb9f6b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21mb/google/hatch/var/kindred: Implement variant_devtree_update()David Wu
This change provides an implementation of variant_devtree_update() for kindred that disable eMMC controller when SKU ID = 1 or 3 BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1 or 3 Change-Id: I8ccb4dae54f223881e0ced9e034bf45b994cc6f2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-21mb/google/hatch: expose get_board_sku() as globalDavid Wu
BUG=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I217e13acd337034554ff055e8bf5011558d1f8bf Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/hatch: Add support for variant_devtree_update()David Wu
This change adds support for variant_devtree_update() that allows variant to update device tree. BUG=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I0e9ad360b6c02c83fe49387ce7bc66d56448ffb9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/eve: Enable wake from MKBP events in S3Aseda Aboagye
We would like to wake eve up in suspend from an MKBP event. This commit simply enables MKBP events to wake the system in suspend using the existing host event interface. There is an accompanying series of patches in the EC firmware for eve that will allow a MKBP wake mask to be configured. BUG=chromium:786721 BRANCH=firmware-eve-9584.B TEST=Build and flash eve, generate MKBP events on the EC and verify that the system wakes up in suspend. Change-Id: I75b05c83a4204d55df11589299a7488d04bbd073 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34454 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19mb/google/octopus: Disable unused USB devicesKarthikeyan Ramasubramanian
Disable unused USB devices in the device tree so that the concerned ACPI objects do not get exported to the OS. BUG=b:133513961 BRANCH=octopus TEST=Boot to ChromeOS. Ensure that the USB devices are disabled based on port status and the concerned ACPI objects are not exported. Change-Id: I0faccdfb8a9df9ec52130437433b15973e3d6f1a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-19mb/google/octopus: Add ACPI configuration for USB devicesKarthikeyan Ramasubramanian
Add devicetree configuration for USB devices so that USB Port Capabilities (_UPC) and Physical Location of Device (_PLD) ACPI objects can be exported to the OS. BUG=b:133513961 BRANCH=octopus TEST=Boot to ChromeOS. Ensure that the _UPC & _PLD ACPI objects are exported for the configured USB devices in the SSDT table. Change-Id: I832ffe305d256296b7447035c5e5dcafb7c296d9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-19google/nocturne: Add MKBP events as a wake sourceAseda Aboagye
We would like to wake nocturne up in suspend from an MKBP event. On Nocturne, MKBP events are notified to the host via a GPIO from the EC, EC_INT_L. However, the AP cannot wake from suspend from this GPIO. Therefore, we'll use the host event interface to wake the system instead. This commit simply enables MKBP events to wake the system in suspend. BUG=chromium:786721 BRANCH=firmware-nocturne-10984.B TEST=Build and flash nocturne, generate MKBP events on the EC and verify that the system wakes up in suspend. Change-Id: I6aff4d38051c939257533229fd0085e42c01d02f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-19mb/google/hatch: Fix SD card is detected as read only issueSubrata Banik
This patch configures GPIO pin GPP_G7 as NF1 with internal pull down. As per schematics SD host controller SD_WP pin is not connected to uSD card connector. Configured gpio pin as NF1 with internal pull down in order to overcome gpio default state in hatch which makes SoC SD_WP pin is enable. BUG=b:137729527 BRANCH=None TEST=Able to write/read data to/from sd card after mounting card device. Change-Id: I0187267670e1dea3e1d5e83d0b29967714d6065e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34396 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19mb/google/helios: Add ALC1011 in device tree to enable speaker ampsSathya Prakash M R
Following changes are done to enable ALC1011 codec on Helios 1. ACL1011 4 devices to I2C4 2. GPIO H13 is set to GPO as per schematics Verified SSDT table and i2cdetect from kernel. Signed-off-by: Naveen Manohar <naveen.m@intel.com> Change-Id: I0d71e3bd2d4493d059a33023c1afe1b630181d4f Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-18soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I53324603c9ece1334c6e09d51338084166f7a585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18mb/google/hatch/var/helios: Implement variant_memory_sku()Furquan Shaikh
This change provides an implementation of variant_memory_sku() for helios that overrides memory ID 3 and 4 to 0 and 1 to workaround the incorrect memory straps in hardware for board id 0 and unknown. BUG=b:133455595 Change-Id: I38fab1f91decac5d0a146e5a6c74e88f677af305 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-18mb/google/hatch: Add support for variant_memory_sku()Furquan Shaikh
This change adds support for variant_memory_sku() that allows variant to return memory SKU ID. Current implementation of memory_sku() is renamed to weak implementation of variant_memory_sku(). Functionally this change should be the same as before for all hatch variants. This function will be overriden by helios in a follow-up CL. BUG=b:133455595 Change-Id: I509c263ec08e0060c12ef1ea9fed673f1e3f3a41 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-18mb/*/*/gpio: Use static for const structuresPeter Lemenkov
Autoport generates these structures as static so let's make it consistent. See also commit 128205fd with Change-Id I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 ("autoport/bd82x6x.go: Improve gpio.c generation"). Change-Id: I4e07bd755ca4a65b76c69625d235a879fe7b43cb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33524 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18mb/google/hatch: Add FP MCU to kohaku device treeShelley Chen
BUG=b:137654283 BRANCH=None TEST=Make sure can see FP MCU spidev in dmesg on bootup Change-Id: Iffa13f29e1abdf430e8dc4a0ee1a931a9e69168c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34371 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18mb/google/hatch: Disable wireless chargingSubrata Banik
This patch makes VGPIO_3 GPIO PIN output and low independent of cnvi is connected or not. BUG=b:123062346 BRANCH=None TEST=boot up Hatch device and make sure VGPIO_3 gpio pin is driven low. Change-Id: I629b99676f56747de1b244724709e14069250097 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34376 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16mb/google/hatch: Disable Bluetooth in bootblock and enable in ramstageShelley Chen
Currently, bluetooth FW is not loaded after a reboot. In order to do this, we have to disable the bluetooth disable gpio (GPP_C14) in bootblock and re-enable it in ramstage. BUG=b:137307516 BRANCH=None TEST=boot up Hatch device and make sure (in dmesg) that proper bluetooth FW in loaded Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16mb/google/octopus/variants/garg: support LTE power sequenceMarco Chen
GPIOs related to power sequnce are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:137033609 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-16mb/google/octopus: add variant_smi_sleepMarco Chen
Allow variants to customize their own smi sleep flow. BUG=b:137033609 BRANCH=octopus TEST=built Change-Id: I75db544d333a640848da9072878687c802c1c1a4 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34340 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16mb/google/octopus: add variant_early_override_gpio_tableMarco Chen
Allow variants to override GPIO configurations of baseboard in the bootblock stage. BUG=b:137033609 BRANCH=octopus TEST=built Change-Id: I18d380cdf58f0f24e1bb1bff394ed8a91188a22c Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-16mediatek/mt8183: add a new configuration for KodamaPeichao Wang
These configuration files can be used to build Kodama firmware. BUG=b:135490566 TEST=check variant: kodama via make menuconfig; make -j Change-Id: I72e80e800ba041df1dda2b0f84470d1ef58bc946 Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33616 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-15mb/google/sarien/variants/arcada: Set data hold time for touchpadCasper Chang
Elan's touchpad requires min 0.3us data hold time. To fine tune the data hold time of i2c1 to meet specification of Elan's touchpad. BUG=None BRANCH=None TEST=Verified data hold time of i2c1 is around 320ns Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I0fa9db3b50e74f193261be96bd9e305bb19841e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Crews <ncrews@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-07-13mb/google/hatch: Fix trackpad configuration in overridetreeFurquan Shaikh
Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix overridetree.cb to advertise the right IRQ. Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248 Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13mb/google/octopus: Add custom SAR values for BluebirdSeunghwan Kim
Bluebird needs to use different SAR values than Casta. Bluebird sku id is 2. CQ-DEPEND=CL:*1435310 BUG=b:129725065 BRANCH=octopus TEST=build Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Update AC/DC loadline valuesRizwan Qureshi
Update the AC/DC loadline values for all domains. Using the same values as in arcada. BUG=None BRANCH=None TEST=Build and Boot hatch EVT Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11google/kukui: Adjust LCM ID voltagesYu-Ping Wu
Currently some of the LCM ID voltage gaps are below 100mV. For example, the voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of misrecognition from the hardware level, the voltages are adjusted so that all the voltage gaps are larger than 100mV. The RD2 resistor values are also updated. BUG=b:136987483 TEST=emerge-kukui coreboot Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192 Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11board/kukui: Remove ADC tolerance from boardidHung-Te Lin
The tolerance of ADC is +-10mV, but the resistors may also introduce 1% variation, and causing the final measured voltage to vary around 5%. By the advisory from hardware team, checking the tolerance seems not really solving or helping anything so we should just ignore that and try to find best matched ID (this also aligns to what Gru did). BUG=b:136990271 TEST=Booted on Krane and no longer seeing ADC out of range BRANCH=None Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: You-Cheng Syu <youcheng@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch/variants: Fix nonworking touch padFrank_Chu
Correct ELAN Touch pad IRQ GPIO to GPP_A21 BUG=b:135507215 BRANCH=none TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33954 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Enable/disable GPIO clock gatingTim Wawrzynczak
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called. Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11mb/google/hatch: Enable LPIT inclusion in DSDTTim Wawrzynczak
Include the lpit.asl file in Hatch's DSDT definition. BUG=b:130764684 BRANCH=none TEST=S3 suspend/resume and S0ix entry/exit work correctly. Ran > 200 iterations of suspend_stress_test and no issues found. Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-11mb/google/hatch: Disable GPIO community dynamic clock gatingTim Wawrzynczak
The dynamic clock gating is causing boards to miss interrupts whose pulses are shorter than 4us. Disable it using FSP UPDs. BUG=b:130764684 BRANCH=none TEST=Compiles Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-11mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)Furquan Shaikh
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since it needs to trigger on both edges. With GPIO IRQ, it is necessary to configure the trigger type in coreboot to match the ACPI configuration. This is because: 1. ACPI configuration is used by intel-pinctrl driver in Linux kernel to re-configure the trigger type for the pad in GPIO DW0 config register. This is done when kernel driver probes and requests irq for its device. 2. On resume from S3, the pad configuration gets reset and coreboot sets the trigger type to LEVEL. However, kernel driver does not probe again. This results in the trigger type being configured incorrectly. This change updates the GPIO configuration for GPP_H0 to set the same trigger type as advertised in ACPI for the kernel. BUG=b:132672011 TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0 works fine on boot as well as after suspend/resume. Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 02:35:03 +0000