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2020-04-24mb/google/hatch: Change baseboard EC wake & SCI masks to match kohakuTim Wawrzynczak
1) Allows MKBP events from the EC to wake the system from suspend states. 2) Remove EC_HOST_EVENT_MKBP from the EC_SCI_EVENTS mask, so that MKBP events don't generate an SCI. The EC is also being changed to use host events to wake up the system, and use the EC_INT_L line for MKBP IRQ signalling. Otherwise, there would be two IRQs generated for MKBP events. BUG=b:148976961 BRANCH=firmware-hatch-12672.B TEST=Verify MKBP events wake system TEST=Verify MKBP IRQs are run Change-Id: I8420a996cb1975007cbbbefe9e2f8f1fca91b666 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shelley Chen <shchen@google.com>
2020-04-24mb/google/hatch: Make Kconfig LAPTOP knob transitively selectEdward O'Callaghan
BUG=b:154071868 BRANCH=none TEST=builds Change-Id: I9c602476a80a97438af01e3c48fac385532373a4 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-24mb/google/hatch: Add Duffy variant specific DPTF parametersEdward O'Callaghan
Copy over DPTF parameters from Puff. BUG=b:153589525 BRANCH=none TEST=none Change-Id: Ic619826205be06f30055fbbc537f3d302dd039bd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40423 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-24mb/google/hatch: Add Kaisa variant specific DPTF parametersEdward O'Callaghan
Copy over DPTF parameters from Puff. BUG=b:153589525 BRANCH=none TEST=none Change-Id: I7270db1283a9c0ee4746da038020e432aeb6dc5e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40422 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23mb/google/nyan*: Always add RTC driverPatrick Georgi
The device is always there, the Chromium OS configs always enable it, so let's mirror that here for a better out of the box experience. Change-Id: Ia2073ee7ecbdb37473e1f1002bc9ae0f7df58e42 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40657 Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23mb/google/smaug: Always add RTC driverPatrick Georgi
The device is always there, the Chromium OS config always enables it, so let's mirror that here for a better out of the box experience. Change-Id: Ic43a314aaed635ae2943df02abc5d163cc3c4ffd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40658 Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23src/mainboard: Const'ify pci_devfn_t devicesElyes HAOUAS
Change-Id: I5bb1a819475383719dbda32d9b5fea63da1e6713 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-23mb/google/puff: Switch USB2 port1 and port3Tim Chen
Switch USB2 port1 and port3 for duffy and kaisa due to circuit change. BUG=b:153682207, b:154451230, b:154445635 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage boot on puff board Change-Id: I9c0cbcbefd045085fb70cf4f41869ab9b98103c4 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-04-23rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGEJulius Werner
When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the appropriate calling stage (bootblock or romstage). This means that ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE are 1. This keeps tripping up people who are just trying to write a simple "are we in verstage (i.e. wherever the vboot init logic runs)" check, e.g. for TPM init functions which may run in "verstage" or ramstage depending on whether vboot is enabled. Those checks will not work as intended for CONFIG_SEPARATE_VERSTAGE=n. This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to clarify that this macro can really only be used to check whether code is running in a *separate* verstage, and clue people in that they may need to cover the linked-in verstage case as well. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-23Puff: Enable VBOOT_EARLY_EC_SYNCDaisuke Nojiri
Romstage is now where software sync is performed for chromebooks. EFS2 has been ported to romstage from Depthcharge. Puff should follow. This patch enables CONFIG_EARLY_EC_SYNC and disables CONFIG_VBOOT_EC_EFS. EFS2 will be done in romstage. BUG=b:147298634, chromium:1045217 BRANCH=none TEST=Verify software sync succeeds on Puff. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I8d7c25f8281496c7adb282f5d4e0fc192d746e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40390 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22mb/google/kukui: kakadu: update the EDID and sequenceScott Chao
The EDID and command sequence are from BOE, the vendor. BUG=b:148997748 TEST=Boots on Chromebook Kakadu and displayed developer firmware screen successfully. Change-Id: Ieb510cb28882afc5b8023c2a57b31187e4a09fbd Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40396 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22mb/google/puff: comment schematics changes for USBKangheui Won
USB routing has changed on reference schematics after Puff rev1 has built. This may confuse people trying to c&p devicetree from the Puff. So add comment to clearly note that there was change, hopefully preventing c&p errors. BUG=b:153682207 BRANCH=None TEST=None Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I5c43a5c04c81b6708c9eeabc48ef11961d7c8561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40546 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22mb/google/deltaur: Correct SPD SMBus addressEric Lai
SMBus uses 7-bits address, change it from 8-bits to 7-bits. BUG=b:151702387 TEST=Check Memory SPD data is correct in console log. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1720b4d6aa0bc785ad86234b3523bb0676ec5c82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-22mb/google/deltaur: Remove GbE FMAP regionTim Wawrzynczak
Deltan will be using the integrated Intel GbE for LAN functionality. Deltaur will not have a LAN port, and so does not need the GbE region. This patch adds a new FMAP descriptor file which explicitly supports the GbE region (chromeos-gbe.fmd), and removes the GbE region from chromeos.fmd. Deltan is then assigned chromeos-gbe.fmd, and Deltaur is assigned chromeos.fmd. BUG=b:150165131 TEST=emerge-deltaur coreboot chromeos-bootimage and use ifdtool -p tgl -t image-delta{ur,n}.bin to make sure FMAP aligns with IFWI Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib93d5ba7f8dbf273ba7c1163022661ede1f44ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22nb/intel/haswell: Deprecate WDB params in pei_dataAngel Pons
The WDB (Write Data Buffer) is a data region in CAR, used as a scratchpad in the read and write training algorithms of memory initialization. Both SNB and IVB use this buffer, but HSW does not. Unlike earlier chipsets, Haswell contains much more in-hardware memory training machinery, known as REUT (Robust Electrical Unified Testing). Among other changes, the REUT hardware has a pattern storage buffer, which renders the need for a pattern storage buffer in CAR obsolete. Deprecate the WDB-related parameters in the pei_data structure for Haswell, as they are leftovers from the previous generation's MRC. Remove them from the mainboards, and explain why they are not required. Because the MRC ABI has to remain the same, the layout of pei_data must not be changed, so rename the WDB parameters instead of deleting them. Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf. Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-04-21mb/google/puff: configure USB PLD groupsPeter Marheine
Each physical port should have the same group and position for both USB2 and USB3, but puff and its variants use different layout than the baseboard so they must override PLD. Ports are split into two groups for front and back, with positions in each group numbered from left to right. BUG=b:151579409 BRANCH=none TEST=PLD_GroupToken and PLD_GroupPosition are set as expected in SSDT. Change-Id: Ibe19e4faa1fbc7117687d789e9bd5584852a48c0 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-20security/vboot, mb/google: Fix build errorsPatrick Georgi
There have been two cases of incompatibilities between overlapping changes, and they need to be resolved in a single commit to unbreak the tree: 1. CB:40389 introduced a new use of write_secdata while CB:40359 removed that function in favor of safe_write. Follow the refactor of the latter in the code introduced by the former. 2. CB:39849 changed google_chromeec_get_usb_pd_power_info()'s interface and adapted all its users. Except for duffy and kaisa which were only added in CB:40223 and CB:40393 respectively, so reapply the patch to puff's mainboard.c to their mainboard.c files. Change-Id: Ib8dfcd61bb79e0a487eaa60e719bd93561f2d97a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-04-20mb/google/hatch/vr/puff: Add psys_pmax calculationGaggery Tsai
This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I8ea01f856411e05a533489280fc2b4a46a1440c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-20mb/google/deltaur: Add memory topology SODIMM and MEMORYDOWNEric Lai
Update memory topology for spd info. Deltan supports SODIMM and Deltaur supports MEMORYDOWN. BUG=b:151702387 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If314894325d6f222807030a36f8c4cefecfe5bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-20google/chromeec: Revise parameters of EC USB PD API callGaggery Tsai
This patch adds voltage and curent parameters in google_chromeec_get_usb_pd_power_info and remove power parameter. Caller could use the voltage and current information to calculate charger power rating. The reason for this change is, some applications need the voltage information to calculate correct system power eg PsysPmax. BUG=b:151972149 TEST=emerge-puff coreboot; emerge-fizz coreboot Change-Id: I11efe6f45f2f929fcb2763d192268e677d7426cb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-20soc/intel/tigerlake: Update iDisp Link UPD settingsSrinidhi N Kaushik
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings. BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jairaj Arava <jairaj.arava@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/deltaur: Correct H1 I2C gpio pin settingEric Lai
H1 uses I2C3 in the HW schematics and connects to GPP_H6 and GPP_H7. Previous setting was wrong so correct it. BUG=b:150165131 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I43c18baea66b927d51689579a40a53f72b94ef36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40487 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/volteer: add ec device entry to devicetreeNick Vaccaro
BUG=b:154279851 TEST=none Change-Id: Ibb56d97d5180ab199c52119135f7eff265908667 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-20mb/google/dedede: Disable dynamic clock gating for cr50's GPIOIan Feng
Disable dynamic clock gating for the community cr50's IRQ lives on. That IRQ is pulsed very quickly, and with clock gating enabled pulses tend to be missed. This is expecially true on the default 0.0.22 firmware that cr50 comes with out of the factory. BUG=b:154178408 b:154293730 BRANCH=None TEST=build waddledoo successful and Linux has no TPM IRQ timeout error. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2b1b3ee59ebf6adce0653e7550b457e02d3c87df Reviewed-on: https://review.coreboot.org/c/coreboot/+/40480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-20mb/google/dedede: Read DRAM population strapKarthikeyan Ramasubramanian
Configure DRAM population strap GPIO according to the schematics. Configure an internal pull-up to support the boards in which the strap is not populated. Read the strap and pass that information to FSP for memory initialization. BUG=b:152275658, b:154301008 TEST=Build and boot the mainboard. Ensure that the strap information is read as expected and passed to FSP. Change-Id: I69583f35ffc219bae9ce06bd4ba9898ed0d4d21d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39812 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/volteer: Update devicetree based on EDSWonkyu Kim
Update device enable/disable based on PCH EDS#576591 vol1 rev1.2 BRANCH=none BUG=b:154037185 TEST= boot up OS in volteer and check and check lspci Unsupported IP should be visable from lspci result Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I61a328da1014ab7584c3ec789971a106c7a0a403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40394 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/dedede: remove samsung-K4U6E3S4AA-MGCL.spd.hexMarco Chen
The samsung-K4U6E3S4AA-MGCL.spd.hex is not used and planed by anyone yet. On the other hand, the spd content is not correct based on JSL spec as well. BUG=b:153426401 TEST=build waddledoo and waddledee successfully. Change-Id: If71e3ef2e3385378633549bf8709a1cd6ecc0dd3 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-20mb/google/deltaur: Enable Cirque touchpad for DeltanEric Lai
Reference Arcada to add device tree for Cirque touchpad. BUG=b:152931802 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia354702c8054b5826d45896f7bff268335726028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-20mb/google/drallion: Increase Melfas touchscreen stop delay to 115msJohn Su
Modify stop_delay as 115ms to waiting for Melfas device I2C interface ready after touch fw auto update and rebind driver. BUG=b:153708773 BRANCH=drallion Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ib392190d2b4188ee228d8ca4873e03176d2f127f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40357 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16mb/google/hatch/var/kindred: Override VBT selection for kledDavid Wu
Override VBT to fix CRC error issue with psr2 panel for kled. Cq-Depend: chrome-internal:2877637 BUG=b:145963505 BRANCH=hatch TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: If201d449e910f80dc514c142aec4808a44fa31a9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-04-16mb/google/puff: Add variant specific DPTF parametersTim Chen
Modify DPTF parameters for OEM EVT build from thermal team. BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-15mb/google/hatch: Add Kaisa variantAndrew McRae
A verbatim copy of variants/puff V.2: rebased on duffy. BUG=b:152951180 BRANCH=none TEST=none Change-Id: I7ea28e96c8b6867e17097a8bfab848928195654d Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-04-15mb/google/hatch: Add Duffy variantEdward O'Callaghan
A verbatim copy of variants/puff. BUG=b:152951181 BRANCH=none TEST=none Change-Id: I9ac262bba60a8d0059722e947ed1b47dddb94f55 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40223 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15trogdor: add support for Bubs variantT Michael Turney
Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15mb/google/puff: Fix up WLAN_OFF gpio configurationEdward O'Callaghan
BUG=b:152927525 BRANCH=none TEST=builds Change-Id: I691377624c870eb0fc6f7e84a4b9cd50b7b09654 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-04-15mainboard/puff: Tune ALC5682I rise_fall times on i2cEdward O'Callaghan
Tunes the headphone amp i2c with measured signal shape. BUG=b:147192377 BRANCH=none TEST=builds and measured i2c frequency below 400khz Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-14trogdor: Add third RAM_CODE pinJulius Werner
We decided to add a third RAM_CODE pin to the Trogdor family for devices after rev1. This patch adds support to read it. Since the newly used pin was previously unconnected (not pulled down) on rev1, this will change the RAM_CODE result for previous versions (and actually make it undetermined until we enable tri-state). But since we're not actually using RAM_CODE for anything yet, and since those are development revisions that will eventually be discontinued, this should be fine. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-04-14mb/google/nightfury: Update tdp_pl1_override valueSeunghwan Kim
Update tdp_pl1_override value to 15W for CML-U based nightfury platform. BUG=None BRANCH=firmware-hatch-12672.B TEST=Built Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Ib0155b961b9d304bed2e9456c4964ebd598af4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/40323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-14mb/google/deltaur: Enable Melfas touch screen for DeltanEric Lai
Reference Drallion to add device tree for Melfas touch screen. BUG=b:152924290 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-14mb/google/octopus/variants/lick: Disable xHCI compliance modeJulia Tsai
Since the first LFPS timeout causes xHCI to enter compliance mode, the SS hub cannot be enumerated. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:153782196 TEST=Verified usb operation successfully. Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> Change-Id: If0bf68c8cf0a2a3b857395b6b82e46cc384ba65c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39874 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/dedede: Enable ELAN touchscreen for WaddledooDtrain Hsu
Add ELAN EKTH6918 USI touchscreen support. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I030c7d7e76a9705be06fe907c4ac279e247cb163 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-14mb/google/dedede: Enable SIS touchscreen for WaddledooDtrain Hsu
Add SiS9813 USI touchscreen support. BUG=b:152936541 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Id04c46c763fdf68418bf2e97be4c8bb6bb73c749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40250 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/hatch: Use tabs for alignmentPaul Menzel
Change-Id: I38d429245810f64a03253b5076391af843f8d0de Fixes: e2ac5b7a36 ("mb/google/hatch/variants: Add DPTF based Fan control") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14mb/google/poppy/variants/nami: Use tabs for alignmentPaul Menzel
Change-Id: Ia707295c55ce2e18eb8970506be10b7b0f3fbc39 Fixes: b77cbbe1b0 ("mb/google/poppy/variants/nami: Update DPTF table") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14mb/google/volteer: Enable RP LTR settingWonkyu Kim
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14mb/google/volteer: fix incorrect fields in SPDsNick Vaccaro
According to Intel Document #616599, 1) SPD byte offset #5 for Tiger Lake should be "0x21" (16 rows, 10 columns) 2) SPD byte offset #13 for Tiger Lake should be "0x01" (1 channel x16) This change fixes those two values in the existing SPD files for Volteer, and zero's byte 9 (bytes 8-11 should be zero'd out in a generic SPD). BUG=b:152827558 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot Volteer to kernel. Change-Id: Ice6a32a2b3827cf99d8e109731ffd9efabf68de1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-04-14mb/google/volteer: fix CROS_GPIO_WP_AH exportNick Vaccaro
Fix GPIO_PCH_WP (GPP_B11) to associate GPP_PCH_WP with community zero instead of community 1. BUG=b:152876091 TEST="emerge-volteer coreboot chromeos-bootimage", flash, boot to and log into Volteer kernel, execute "wp enable" in H1 console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in H1 console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: I082154efd72459ec54999ed7c7bb7420a38f7b6e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-13mb/google/deltaur: Add support to enable GbE on variantVarun Joshi
- Configure devicetree for enabling GbE on variant and remove from baseboard. - Configure Kconfig to enable GbE region. - Configure fmd to incorporate GbE. BUG=b:151102809 Cq-Depend: chrome-internal:2843183 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I1c36b132546049e3e775585c41164072f4ece73e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2020-04-13mb/google/deltaur: Return SKU ID infoAnil Kumar
For Deltaur and Deltan variants return proper SKU ID based on EC firmware type and sensor detect GPIO value BUG=b:152544516 TEST=make build successful for deltan Change-Id: I20a497739e5062400b093648c3a634203dec6105 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-13mb/google/deltaur: Update onboard memory configVarun Joshi
Update dq, dqs map based on deltan schematics. Configure memory to read SPD. BUG=b:151702387 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 19:59:01 +0000