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2020-06-22mb/google/hatch: Stop AP power-off on Puff & variants cr50 updatesEdward O'Callaghan
Fix Puff and its variants to not shutdown the AP before the cr50 reboot. This is the same approach that Sarien do to remain on during a cr50 cycle. BUG=b:154071064 BRANCH=none TEST=none Change-Id: I5f92b4f769654b67c10c91e4cc7b2bce785e302f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42497 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/hatch: Make puff and variants share common dptf.aslEdward O'Callaghan
Here we consolidate some of the dptf.asl duplication between Puff and it's variants. Customizations can be done later either as a direct copy or preferably via introducing a #define. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I35fa1e152adb5f04fb6ef1bd2448376cf9f37980 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-22mb/google/hatch: Make puff and variants share common ec.hEdward O'Callaghan
Here we consolidate some of the ec.h duplication between Puff and it's variants. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I13dfe09da5c7a19677b156063bb51a58bc059b93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-06-20mb/google/jecht: Correct hda_verb mic pin configsMatt DeVillier
Commit 0148fcb4 [Combine Broadwell Chromeboxes using variant board scheme] incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19, so set them back to the correct values, which match the original Chromium sources (where the NID identifiers in the pin config comments were reversed, which was the source of the confusion originally. Test: build/boot guado variant, verify mic attached to 3.5mm jack functional Change-Id: I65b813c8f801303682762ce5a7446e07af117b9f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42518 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-20mb/google/beltino/**/hda_verb.c: Correct mic pin configsMatt DeVillier
Commit 0558d0c [mb/google/beltino/**/hda_verb.c: Correct pin configs] incorrectly flipped the mic pin configs for verb NIDs 0x18 and 0x19, so set them back to the correct values, which match the original Chromium sources (where the NID identifiers in the pin config comments were reversed, which was the source of the confusion originally. Test: build/boot panther and zako variants, verify mic attached to 3.5mm jack functional Change-Id: I172a0bb299049d113a0272ee9c790b25b6242cad Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42499 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-20mb/google/zork: rename fch_apic_routing struct to fch_irq_routingFelix Held
fch_apic_routing is used as name of an array that init_tables() populates with the APIC IRQ routing information. Also the fch_pirq array where fch_apic_routing was used as struct name contains the IRQ mapping for both PIC and APIC mode, so rename it to fch_irq_routing. Change-Id: Iba7a2416c6e07cde1b8618bdabf31b00e3ca4dd1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-20mb/google/zork: remove redundant IRQ routing configurationFelix Held
The PIC and APIC IRQ routing tables are pre-populated with PIRQ_NC in init_tables(), so the fch_pirq table entries where both IRQ numbers are set to fch_pirq are redundant and can be removed. Change-Id: I0d9b4f25e12a66cf86d1ad541955c3d2fe336c5a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-19soc/amd: move acpi_wake_source.asl to common directoryFelix Held
Files are both identical and common for both SoCs. Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19mb/google/zork: Disable UART 1, 2 and 3Raul E Rangel
We don't use these on zork, so lets save the power. BUG=b:153001807 TEST=Boot OS and make sure UART 1, 2 and 3 are not probed and remain powered off. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2fadeba779b66ec2fb13951b9487118ef0737a94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-19tigerlake: add unique acpi device ids for dptfSumeet R Pawnikar
Add unique new acpi device ids for dptf for Tiger Lake soc based platforms and update volteer speficic dsdt.asl file accordingly. The Linux kernel driver expects these new acpi device ids for dptf functionalities. BUG=None BRANCH=None TEST=Build and boot on volteer system Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-19mb/*/*/Kconfig: guard board name in quotesPatrick Georgi
New kconfig dislikes unquoted slashes. Change-Id: Ief242de081071021b9c904a24535d025f6674270 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42480 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18mb/google/dedede: Add support for 16 MiB flash map descriptorKarthikeyan Ramasubramanian
Upcoming variant boards will use 16 MiB SPI ROM. So add support for 16 MiB flash map descriptor. BUG=b:155107866,b:152981693 TEST=Build different variant boards. Ensure that waddledoo which is using 32 MiB SPI ROM boots. Cq-Depend: chrome-internal:3107306 Change-Id: I8a6868da3280a662ff3a30623804ff135e6cbfbc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-18mb/google: remove cannonlake dptf.asl include file from dsdt filesSumeet R Pawnikar
Remove cannonlake dptf.asl include file from all the dsdt files as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on the system Change-Id: I961a3ecb27e7bb7bb0b98c8630900bada0531639 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18mb/google/hatch: fix variants' selection of CHROMEOS_DSM_CALIBMatt DeVillier
CHROMEOS_DSM_CALIB requires/selects CHROMEOS, so only select if CHROMEOS already selected, otherwise building for non-ChromeOS targets fails. Test: build HELIOS for non-ChromeOS target (Tianocore payload) Change-Id: Ic0fd3b0a0efbc5a1f6896eb379569a55cb0f67f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-18mb/google/volteer/variants/terrador: Disable EC SW syncDavid Wu
It is the reference board of TGL-Y platform, we want to disable EC SW sync for Proto stage, it would be re-enabled before EVT stage. BUG=b:156435028 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie7999e24e9c173d4870b35ce1728f3dcc8dcac29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/google/volteer: remove unused GPP_H23Nick Vaccaro
BUG=b:157567939 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel. Change-Id: I3046cf3a359e833a5d204f78ab84312e8665061f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42411 Reviewed-by: Jes Klinke <jbk@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/volteer: Set IomTypeCPortPadCfg default to 0x09000000Brandon Breitenstein
Temporary workaround for S0ix issues related to FSP's handling of 0 value. When IomTypeCPortPadCfg is 0 FSP completely skips any flow related to this value which seems to be causing issues with s0ix. This is still being debugged and a final solution will be made when available BUG=b:159151238 TEST=flash image with workaround to volteer and verify that s0ix cycles correctly. Change-Id: Id79dd1c49958389cdb666b3760abd821bc1973a8 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42268 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17soc/amd/picasso: rename PICASSO_UART Kconfig optionFelix Held
The PICASSO_UART Kconfig option is about using the internal MMIO UART controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-17mb/google/hatch: mushu: Add F75303 temp sensor to dptfPuthikorn Voravootivat
Update the following in dptf.asl - Add support for TSR3 - Change TSR0/TSR1/TSR2/TSR3 From: Charger, 5V, GPU , None To: Charger, GPU, F75303_GPU, F75303_GPU_POWER - Adjust fan/cpu trip point accordingly - Fix formating in dptf.asl - Throttle charger when TSR0 (charger) is hot instead of throttle CPU BUG=b:158676970 BRANCH=None TEST=grep . /sys/class/thermal/thermal_zone5/{type,temp} /sys/class/thermal/thermal_zone5/type:TSR3 /sys/class/thermal/thermal_zone5/temp:50800 Change-Id: Iedbb6bc7c1e59a027119c70791b9bc8a4d83ff87 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42270 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/google/puff: add MST and LSPCON details to variants devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices on kaisa, duffy and noibat. BRANCH=None BUG=b:156546414 TEST=None Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I7b54512cd88e7280374c188315cabc2fba197f69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-15haswell boards: Factor out MAX_CPUSAngel Pons
ULT only has 4 threads, but we are not changing it here to preserve binary reproducibility. Change-Id: I041c5dff2de514244f9c919c4c475cca979c34ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41842 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15sandybridge boards: Factor out MAX_CPUSAngel Pons
Also update autoport accordingly. Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/volteer: Disable HDA PCI device when AUDIO=NONEDuncan Laurie
If there is no installed audio daughter board on volteer then the HDA driver in the kernel will crash on resume. In order to prevent this disable the PCI device when AUDIO=NONE probe match is true. BUG=b:147462631 TEST=boot on volteer and ensure that the PCI device at 0:1f.3 is gone Change-Id: I4a436e1b76418030bf635427e490b54a713fdd33 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14mb/google/zork: Drop OEM_BIN configsFurquan Shaikh
Zork family does not use OEM binary and so this change drops the configs required for adding this binary. Change-Id: Id38c67030e4055ab16934d1a900ee1cea5843b54 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14mb/google/zork: Enable ELOG optionsFurquan Shaikh
This change enables following ELOG options for zork family: ELOG ELOG_BOOT_COUNT ELOG_GSMI ELOG_BOOT_COUNT_CMOS_OFFSET BUG=b:158875638 TEST=Verified that kernel reports GSMI loading correctly: [ 5.308982] gsmi version 1.0 loaded Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4f34a814e744e863f1fbfc19e37209cb7febbdcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14mb/google/volteer/var/terrador: Update dq/dqs mappingsDavid Wu
Update dq/dqs mappings based on terrador schematics. BUG=b:156435028,b:151978872 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I97697a3dd9b88eaffe6e2b1be7bd346979cbc956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14mb/google/volteer: Enable thermal sensor 4 in DPTF for volteerDeepika Punyamurtula
Enables the fourth thermal sensor for fan in DPTF for volteer BRANCH=None BUG=b:149722146 TEST= On volteer system check `cat /sys/class/thermal/thermal_zone5/type` for TSR3 Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: Ie11496828133aa71f1017f759516e2e5d3dff2d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-14mb/google/puff: add MST and LSPCON details to devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices. BRANCH=None BUG=b:156546414 TEST=Manual tested and able to see update on sysfs and ssdt table Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Iaef6c08f241ea671d1487a8524162dbb438b8e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-14mb/google/hatch/vr/puff: Set up PL2 and PsysPL2Tim Chen
This patch adds correct PL2 baseline setting and PsysPL2 for different SKUs. There is no way to identify the barral jack power rating, the assumption is following that ships with the product: 1. i3/i5/i7: 90W BJ 2. Celeron/Pentium: 65W BJ For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the original settings as 90% of adapter rating for PsyspL2/PL4 and PL2 as min(PL2, 0.9n) where n is adapter rating power. BUG=b:143246320 TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct Change-Id: Ib16d4f65707801b430f06892ab45ecfa7551593f Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-14mb/google/fizz: add variant chipset display initJeff Chase
The Endeavour variant does not have a DisplayPort input so there's no need to wait for it. BUG=b:147830399 BRANCH=none TEST=boot endeavour; check coreboot logs Signed-off-by: Jeff Chase <jnchase@google.com> Change-Id: I30c7c47f19a61ce66c6c923864d80870d2761859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-06-14mb/google/dedede: Enable early EC software syncMeera Ravindranath
BUG=none BRANCH=none TEST=Verify sysjump from EC console, EC sync in romstage in AP console and crossystem reflect ecfw_act as RW Change-Id: Ief96fe481c94acef3754881cf1f453699fbfa52e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41396 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/dedede: Select Recovery Cache Kconfig optionMeera Ravindranath
BUG=none BRANCH=none TEST=Boot WaddleDoo in recovery and populate the recovery MRC cache. The subsequent recovery boot should boot out of the stored recovery MRC cache and skip memory training. Change-Id: Ief86fe481c94abef3754881cf1f454699fbfa52e Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41162 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14mb/google/hatch: Switch USB2 port1 and port3 on NoibatEdward O'Callaghan
Switch USB2 port1 and port3 for noibat due to circuit change. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: I711038624f3efe397be73c29a940b3e17802598f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42296 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13mb/google/zork: update DRAM SPD table for vilbozPaul Ma
Add DRAM support for vilboz: Hynix H5AN8G6NCJR-VKC # 0b0000 Hynix H5ANAG6NCMR-VKC # 0b0001 Samsung K4A8G165WC-BCWE # 0b0010 Hynix H5AN8G6NDJR-XNC # 0b0011 Micron MT40A512M16TB-062E-J # 0b0100 Samsung K4AAG165WA-BCWE # 0b0101 Micron MT40A1G16KD-062E-E # 0b0110 BUG=b:157523051 BRANCH=none TEST=build Change-Id: I251fd9cc7bc51bfdeaa577f7034da750e684dc99 Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-12mb/google/volteer/var/voxel: Add memory parts and generate DRAM IDsFurquan Shaikh
This change adds memory parts used by variant voxel to mem_list_variant.txt and generates DRAM IDs allocated to these parts. This variant is not yet supported by coreboot but DRAM IDs need to be generated for it. In the coming days, variant voxel will be added to coreboot. BUG=b:157732528 Change-Id: I8780beec987deb8fed11bb8f84275dcba4768514 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-12mb/google/volteer: Customize PCH VR settings for better Sx power savingsVenkata Krishna Nimmagadda
For Volteer mainboard, this patch set optimized values for PCH external VR settings and ext rail voltage/current, to achieve better power savings in sleep states. v1p05 and vnn power rails can be used as an alternative source by-passing vccin_aux during Sx. This by-pass feature, enables us to shutdown vccin_aux rail which is higher voltage rail compared to v1p05 and vnn. These both rails were disabled by default in FSP. Changes in this patch are: 1. v1p05 and vnn rails are enabled and enabled supported voltage types in S0i1, S0i2, S0i3, S3, S4, S5 states. They were disabled by default. 2. Icc Max for v1p05 changed to 500 mA from default 100 mA. 3. vnn rail's voltage is changed to 5 V from default 4.2 V. BUG=None BRANCH=None TEST="Build and boot volteer and check VR settings with Intel ITP-XDP debugger and verify approx 250 mW power savings in Sx" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ib46423872c956af9aaa92902fce552d5447237c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42223 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/dedede: Add new variant botenPeichao Wang
Add initial support for boten variant board. BUG=b:158023819 BRANCH=None TEST=build Change-Id: I56fe901c6aec781fac217ab08f7583cc25788688 Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-06-12mb/google/hatch: Remove unused USB2 port from NoibatEdward O'Callaghan
This port isn't packed on the board, so remove from the devicetree. BUG=b:154585046,b:156429564 BRANCH=none TEST=none Change-Id: Ib4aee337f67453adcebff7e93e25db7a838e3b2d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42269 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12mb/google/puff: Update i2c[2] and i2c[3] rise and fall timesSam McNally
BRANCH=none BUG=b:158713330 TEST=Flashing the LSPCON firmware works Change-Id: Ib371f6954115145047c70cfd25262026cce087fd Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-11vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structsFelix Held
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor structs isn't needed, since this code is picasso-specific, so drop it. Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-11mb/google/dedede: Add new variant drawciaWisley Chen
Add initial support for drawcia BUG=b:158540280 BRANCH=None TEST=build Change-Id: Ic775bb2a93581e422379ca90127e3581bbf3c89e Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com>
2020-06-11mb/google/volteer: Update DPTF TSR2 sensor ID for volteerDeepika Punyamurtula
Update DPTF_TSR2_SENSOR_ID to 2. Fixes the issue where TSR1 and TSR2 have the same DPTF_TSR#_SENSOR_ID value causing them to report the same temperature under /sys/class/thermal and also swap TSR0 and TSR1 in DTRT to match physical sensor in volteer schematics BRANCH=None BUG=b:149722146 TEST=On volteer system check TSR1 and TSR2 temperatures, should report different values `cat /sys/class/thermal/thermal_zone[3,4]/temp` Also verify other TSRs using `cat /sys/class/thermal/thermal_zone*/temp` and `ectool tempsinfo all ; ectool temps all` Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: Idc5f35e4faf59b0ee726eb32a08eab4654fb342d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42232 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10mb/google/hatch: drop VBOOT_LID_SWITCH from hatch baseboardMatt DeVillier
Selecting VBOOT_LID_SWITCH under BOARD_GOOGLE_BASEBOARD_HATCH creates a requirement for VBOOT, and prevents building in the non-vboot/non-ChromeOS case. As this symbol is already selected by CHROMEOS below, there's no need for the baseboard (and only one of the two) to select it, so don't. Change-Id: I060e82185997bce451648173dd97dd6a3d5d237f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-10mb/google/dedede/variants/waddledoo: Adjust I2Cs CLK to meet specJohn Su
After adjustment on waddledoo Touch Pad CLK: 392.9 KHz Touch Screen CLK: 387.4 KHz Audio CLK: 350.9 KHz BUG=b:151302522 BRANCH=master TEST=emerge-dedede coreboot chromeos-bootimage measure by scope with waddledoo. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iec02a751f1effdbefbb2969db2fd57f27ecdd033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42187 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10mb/google/zork: Set FMDFILE for zork familyFurquan Shaikh
This change sets FMDFILE for zork family so that coreboot builds pick up the right flash layout. BUG=b:155990176 Change-Id: Ia1673622ccd14a2ff7bde555ed33d5b51cf4272a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42106 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10mb/google/dedede: Enable S0ix supportAamir Bohra
Change-Id: I4cadfe69e36f959b54e374800c32629a7481ea94 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-10mb/google/dedede: Add mainboard acpi support for GPIO PM configurationAamir Bohra
Setting the default values for GPIO community power management, causes issues in detecting TPM interrupts. So to avoid that GPIO PM has to be disabled in devicetree. But for S0ix it is needed. This patch implements a workaround in ASL code to enable GPIO PM on S0ix entry and disable it on S0ix exit. This patch adds the following three platform specific methods. 1. MS0X to enable power management features for GPIO communities on low power mode entry and disables it on exit. 2. MPTS to enable power management features for GPIO communities when preparing to sleep. 3. MWAK to disable power management features for GPIO communities on waking up. BUG=b:153847814 TEST=Verify S0ix is working. GPIO PM configuration is upadated on low power mode entry and exit. Change-Id: I7225b78ab2ac5bf17f93230cd85cd21e836d807d Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41502 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09mb/google/volteer: move volteer-specific GPIOs to variant gpio.cNick Vaccaro
- Move the GPIOs that are likely to be volteer-specific (mostly peripherals) to reside in variants/volteer/gpio.c so that variants don't have to override too many GPIO settings. - Modify malefor's gpio.c to adjust for the changes to baseboard's gpio.c. - Remove unused GPP_C3 (USB4_SMB_SCL) and GPP_C4 (USB4_SMB_SCA) settings. - Remove unused GPP_D9, GPP_D10, GPP_D11, and GPP_D12 settings. - Remove unused GPP_E8 (SLP_S0IX), COEX, WWAN, and SNDW related settings for malefor. - Remove unused GPP_R4 (HDA_RST_L) setting. BUG=b:157597158 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer SKU4 to kernel. Change-Id: Ib2f384f539d55a3a8d4a7608336ef22aca3d8c4f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 18:58:37 +0000