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2018-10-24mb/google/poppy/var/nocturne: Use CRFP as device name for FP deviceFurquan Shaikh
This change uses CRFP ACPI name for FP device since user space utilities expect this name for triggering different actions. BUG=b:112974410 BRANCH=nocturne Change-Id: I63309227c916b43917e529c223cf738fc3baa209 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29231 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24mainboard/google/poppy/variants/rammus: Enable touchscreenkane_chen
On rammus, set GPIO GPP_C22 to 1 for touchscreen power on. And add touchscreen device "PNP0C50" to I2C0. According to touchscreen spec, device power on initialization takes 105 ms, so set "generic.enable_delay_ms" to 120. We found there is i2c error log pop up when we set delay time to be 110ms or 105ms. If we set delay time to be 120ms. System will not pop up i2c error log. BUG=b:115944726 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure touchscreen works. Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-24mb/google/octopus: Use DIMM_INFO_PART_NUMBER_SIZE for part_num_storeFurquan Shaikh
This change uses DIMM_INFO_PART_NUMBER_SIZE to decide the size of part_num_store that holds the number of DRAM part. It ensures that host advertises the supported size to read part number from the EC. BUG=b:115697578 Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
2018-10-23mb/google/poppy: add the smi_events backZhuohao Lee
Before entering the OS, the AP relies on the smi handler to shutdown the system when the lid closes. Without the smi_events setting, the AP will not receive the smi handler. As a result, the AP won't shutdown and will always keep in S0. This problem is caused by the https://review.coreboot.org/c/coreboot/+/28983 and this patch adds the smi_events back to support the smi handler for the lid close. BRANCH=master BUG=b:115572596 TEST=test_that -b ${BOARD} ${IP} firmware_ECLidShutdown Change-Id: Id82311a8ccd109f9c26516f59a45bdf34da98529 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/29191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-23mb/kahlee mb/gardenia: Remove smbus.asl includeRichard Spiegel
The file soc/amd/stoneyridge/acpi/smbus.asl has 0 bytes (no content). Remove the include of this file. BUG=b:117814641 TEST=Build grunt and gardenia. Change-Id: I0c48167195a9708afc255490bb1996b6dfc7bdfb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29178 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23mb/google/octopus: Use a single GPIO for trackpad wake and IRQFurquan Shaikh
This change uses the newly added macros for configuring the same GPI pad(GPIO_135) for IRQ (normal interrupt operations) and wake (interrupt for waking from S3/S0ix) for the trackpad device. The other pad GPIO_142 is now configured as not connected. BUG=b:117553222 TEST=Verified that yorp and bobba wake from S3 and S0ix using trackpad. Change-Id: I2b704f1be493141629c647b79723b0025b0f7dd6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22mb/google/poppy/var/nocturne: Change IMX319 sensor link freqLijian Zhao
Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the changes from kernel driver. IMX319 has two PLLs and it can be configured either single or dual. Previous driver implemente dual PLL mode, however image sensor vendor prefer single PLL mode and calculate the pixel rate became easier. So the kernel driver changed to use single pll, coreboot change will match that. Bug=b:116082248 Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28736 Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22mainboard/: Select MISSING_BOARD_RESET appropriatelyNico Huber
We didn't have a hard_reset() implementation for these boards. So select the board_reset() stub for them. Change-Id: I77651e3844632fb1a347008c96e53d23cc5a2646 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29170 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22soc/rockchip/rk3399: Convert to `board_reset()`Nico Huber
Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22reset: Convert individual boards to `board_reset()`Nico Huber
Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-19mb/google/octopus: Preserve MRC training data across firmware updateFurquan Shaikh
This change udpates FMAP to wrap MRC training data in RW_PRESERVE section so that we don't lose the data when performing full firmware updates on octopus. BUG=b:117882029 TEST=Verified that chromeos-firmwareupdate doing full firmware update preserves training data on octopus. Change-Id: I5adb9bfa926327057b003360150685a8b4778c8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-19mb/google/fizz: Provide nhlt variant APIDavid Wu
Move current NHLT configuration implementation to baseboard so that variants can leverage it or provide their own configuration. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I30d93babb6fc09e8642b3740f1f7638fa33f0ade Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Provide cros_gpio variant APIDavid Wu
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I2fa52c005cacdbcc322d107a3ac92d22df3f3697 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Add variant API for gpioDavid Wu
Provide API for gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Provide baseboard and variant conceptsDavid Wu
In order to be able to share code across different fizz variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/fizz - code variants/fizz/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot CQ-DEPEND=CL:1273514 Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19google/grunt: Remove unused MRC regions from FMAPRaul E Rangel
I didn't change the offsets of all the other regions because I didn't want to cause all dogfood devices to lose their corp enrollment. BUG=b:117797131, b:117798830 BRANCH=none TEST=Ran autotest and made sure the tests were skipped /tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache [ PASSED ] /tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache TEST_NA: No RECOVERY_MRC_CACHE was found on DUT. /tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal [ PASSED ] /tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal TEST_NA: No RECOVERY_MRC_CACHE was found on DUT. Change-Id: I5cdbf4139dde80fe6e9d0045139a97841b03bc42 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/29171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-18src/mainboard: Remove unneeded whitespaceElyes HAOUAS
Change-Id: Ibf23f49e7864c611a3cb32a91891b6023a692e1d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18mb/google/glados/variants/sentry: Remove unnneded whitespaceElyes HAOUAS
Change-Id: Ibc928dc66e00dbb40d25420fd92f6c5f8049dec1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28703 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18src/{sb/intel,mb/google/auron}: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I564319506870f75eab58cce535d4e3535a64a993 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18mb: Fix non-local header treated as localElyes HAOUAS
Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-17google/kukui: Configure USBTristan Shieh
Set up USB host controller. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iec98f3dc1bbf3dda3d28dbefad15339d48608c7e Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-17mb/*/*: Clean up FADT checksum assignmentJonathan Neuschäfer
The assignment of header->checksum was in some cases done twice, or unnecessarily split into two lines. Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-10-17mb/google/poppy/variants/nocturne: Disable pull-down of GPP_E9/E10Roy Mingi Park
While these pins were set to a pull-down 20KOhm, NPCX EC consumes ~2.1mW higher power. Becasue there was leakage current on both GPIO67 and GPIO70 from NPCX EC. With the external pull-up 10KOhm for USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current. BUG=b:117139495 TEST=Check nxpc EC power to see power improvement Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/29007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17mb/google/poppy/variants/nocturne: Tune DPTF settings for CPUSumeet R Pawnikar
Update CPU passive temperature threshold value from 70C to 80C, to avoid early throttling for spiky workloads. Also, change CPU throttling interval from 1 sec to 5 sec for CPU temperature. BUG=b:116400298 BRANCH=None TEST=Manual performance testing on nocturne. Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/29044 Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15mb/google/poppy/variants/nami: Disable rear camera/DMIC for SyndraAmanda Huang
Since there are two cameras on Nami and only one camera on Syndra. We need to disable rear camera/DMIC on all Syndra sku. BUG=b:112876867 Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-15vc/google/chromeos/ec: remove EC hibernate in cr50 update pathAaron Durbin
More platforms are not able to hibernate under certain circumstances, such as when AC is plugged. This original path was conservatively put in to prevent potential damage when cr50-update-caused asynchronous resets occur. Julius' compelling argument that async resets from recovery mode requests should have enough coverage of the design over the course of project development. Remove the hibernate path and assume all is well going forward. Change-Id: I37121e75ff4e6abcb41d8534a1eccf0788ce2ea2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/29076 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-12amd/stoneyridge: Rename GppClkCntrl fieldsMarshall Dawson
Make the field names of the MISCx00 GPPClkCntrl more manageable by shortening their names. Make the definitions look more like the rest of the header file. Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-11mb/google/poppy/var/nocturne: Provide override for ec eventinfoFurquan Shaikh
This change implements the callback to provide google_chromeec_event_info structure in nocturne variant and sets MKBP SCI based on board id. BUG=b:112366846,b:112112483,b:112111610 Change-Id: Ifcc10aefc8f450214bd64dfffaf8854ada43f323 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11mb/google/poppy: Allow variants to provide event info at runtimeFurquan Shaikh
This change adds a variant callback to read google_chromeec_event_info from variant at runtime to allow override of any events based on factors like board id. This callback is used in ramstage and smm to get google_chromeec_event_info structure for performing various actions like setting masks and logging wake events from EC. BUG=b:112366846,b:112112483,b:112111610 Change-Id: If89e904c92372530a0f555952f87702f068e0b03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11amd/stoneyridge: Indicate STAPM units in their nameRichard Spiegel
STAPM devicetree registers do not indicate the unit, which causes confusion. More importantly, the time was assumed to be in seconds when it's actually milliseconds. This caused early STAPM configurations to fail. BUG=b:117590953 TEST=Build grunt Change-Id: I2a7e3d43601992d1f7b02456913c763d940fe9ee Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29035 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11mainboard/google/kahlee: Set PSPP setting to BalanceLowAkshu Agrawal
With correct stapm values audio issue is not observed with PsPPBalanceLow (Gen1 speed). BUG=b:117569918 TEST=audio playback multiple times Change-Id: Iaeae52b262b12622a6753432e3fc40bf5f0fd8e0 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/29028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-11mb/google/kahlee: Set stapm parameters with time value fixedAkshu Agrawal
stapm_time passed to smu via agesa is in msec. With earlier value smu was getting stapm_time as 2.5 sec instead of 2500 sec and thus causing issue in S3, and audio in PsppBalanceLow state. BUG=b:117569918, b:117252463 TEST= 1.) audio works with PsppBalanceLow 2.) S3 cycles Change-Id: I673e7e673d042918dff47141f37bbca354f5c45c Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/29027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-11mb/google/octopus: I2C clock tuning for meepWisley Chen
Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the frequency does not exceed 400KHz. BUG=b:117298114 TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency under 400 KHz Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-10mb/google/octopus: Drop I2C bus 0 clock frequency for Phaserpeichao.wang
Need to tune I2C bus 0 clock frequency under the 400KHz since this bus attached the Stylus EMR pen and need meet the spec. Bug=b:117297214 TEST=flash coreboot to the DUT and measure I2C bus 0 clock frequency whether under 400KHz Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28973 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPDChris Zhou
Add SPD file for sdp samsung_dimm_K4AAG165WB-MCRC (ram id: 9) BUG=b:112679174 TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28974 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10mb/google/kahlee/variants/*/devicetree.cb: Reset I2C slavesRichard Spiegel
Use the new I2C slave reset function and reset all slaves connected to all 4 I2C. Do this in all boards. BUG=b:114479395 TEST=Added debug code. Build and boot grunt. Examined output, confirmed GPIO pins changing as required. Removed debug code. Change-Id: Ia78ee5d5319d3c1a7daa9c56c81d435999b3a359 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28575 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10mb/google/kahlee: Add delan variantMartin Roth
BUG=b:117173908 TEST=Build delan Change-Id: If149b8c43ff16637c38d5320eb606bb72d62e953 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-10-10mb/google/fizz: Prepare sharing directory for variantsDavid Wu
Clean up Kconfig file in order to support variants for fizz. Add BOARD_GOOGLE_BASEBOARD_FIZZ that can be set by various fizz variants to use the common baseboard configs. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-09mb/google/kahlee/variants/liara: Update H1/TP/TS i2c timingsChris Zhou
After adjustment on Liara EVT H1: 392.03 KHz TP: 397.87 KHz TS: 397.71 KHz BUG=b:116309237 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage measure by scope Change-Id: Ib5d7ce09ac58f33ee826d7541e1a0d14a03add9a Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-08mainboard/google/kahlee: Set PSPP setting to BalancedHighAkshu Agrawal
Setting default PSPP setting to BalancedLow was causing audio playback issue in most of the units. With BalancedLow either there was no sound or noise on playback. Switching to BalancedHigh as default option. BUG=b:116553085, b:112020107 TEST=Test playback and hear proper audio. Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/28967 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for BobbaPan Sheng-Liang
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 3 for DVT. BUG=b:115697578 TEST=verified it in Bobba EVT board which rework ram id. Change-Id: I0fb457d8772f5038e5d90188d7682956ddfad46b Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28891 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08mb/google/poppy/variant/nocturne: correct wifi wake registerNick Vaccaro
Wifi wake register is incorrectly set in devicetree. Set wifi wake to its correct wake source, GPE0_DW2_01. BUG=b:117330593 TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture, connect wifi to a hotspot, suspend device, echo freeze > /sys/power/state, and then shutdown the hotspot and verify device wakes. Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28938 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08mb/google/poppy/variant/nocturne: Disable WAKE# signalNick Vaccaro
The WAKE# signal has moved to LAN_WAKE, so WAKE# is now floating and must be disabled. This change disables WAKE#. BUG=b:117284700 TEST=none Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-06soc/intel/common, mb/google, mb/siemens: Use lower case x for RXDFurquan Shaikh
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_* macros, this change uses lower case x for *RXD*. It helps avoid confusion when using the macros. Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06mb/google/poppy/var/ampton: Get rid of min board id for DRAM in CBIFurquan Shaikh
All ampton boards should have the DRAM info configured in CBI and so DRAM_PART_NUM_ALWAYS_IN_CBI is already selected for ampton. This change gets rid of the redundant minimum board id value for Ampton. BUG=b:117071184 Change-Id: I59f60b8c5aa34b55b8e473c06cc49ea7ae284d62 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06mb/google/octopus/variants/fleex: Disable I2C0 in devicetreeFurquan Shaikh
Fleex does not have any device on I2C0 and hence this change disables I2C0 device (16.0) in devicetree and gets rid of the I2C tuning parameters for I2C0. BUG=b:115600671 Change-Id: Ib799eae05b667cee2272bbd37f0ca44b7cec66cd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06mb/google/octopus: Disable I2C3 in devicetreeFurquan Shaikh
I2C3 is connected to the debug header and won't be required unless connecting the debugger. This change disables I2C3 device (16.3) in devicetree. Change-Id: I650fa040075119a21864c83d8470dd2155c9edb9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-10-06mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSDFurquan Shaikh
This change uses the generic device driver to provide DMIC properties in ACPI table to the OS driver. BUG=b:112888584 Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28797 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-09 17:32:07 +0000