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2020-08-24mb/google/dedede/var/drawcia: Add Goodix touchscreenWisley Chen
BUG=b:155002684 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I89a4a5bbcd26b156a9660f80090bb5c953196b84 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-24mb/google/volteer/var/terrador: Add PMC.MUX.CONx devices to devicetreeDavid Wu
Add PMC.MUX.CONx devices to devicetree for terrador. BUG=b:164941862 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3f5ea4c0fbcc0117934a1ec1c350e867d881eb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-24mb/google/volteer/var/todor: Add PMC.MUX.CONx devices to devicetreeDavid Wu
Add PMC.MUX.CONx devices to devicetree for todor. BUG=b:164941862 TEST=FW_NAME=todor emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iaef603553597685b03e805603352f38d70d65a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-24mb/google/zork: update telemetry settings for woomaxChris Wang
update telemetry value with the SDLE test result. BUG=b:158964769 BRANCH=none TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic419ca5ca00e4e8602dbc12212a8a63ed3657e02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24mb/google/zork: Fix GPIO table for v3.6 schematics for woomaxKane Chen
Add board version switch GPIO table on gpio.c. BUG=b:165887084 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I661e16f7b4769e83450f41ff267c0d253441c4cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24mb/google/zork: Enable WiFi SAR configsKevin Chiu
BUG=b:159304570 BRANCH=master TEST=1. cros-workon-zork start coreboot-private-files-zork 2. emerge-zork chromeos-config coreboot-private-files-zork \ coreboot chromeos-bootimage Change-Id: Ibf1cca8a039e37acbbd9f97ee6a35414ceb3ca6e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24mb/google/dedede: add mainboard_smi_espi_handler for dedede.Kane Chen
By adding mainboard_smi_espi_handler, the espi smi can be handled properly. BUG=b:163382105 TEST=Tested lid close smi can be handled properly in depthcharge stage Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I8a2ecb52d5f6586f8acd57c4965b4238b95e3b64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44564 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 8GB support for burnet/escheKevin Chiu
Add LPDDR4x DRAM index#6 MT53E2G32D4NQ-046 8GB BUG=b:159301679 BRANCH=master TEST=1. emerge-jacuzzi coreboot 2. MT53E2G32D4NQ-046 8GB M/B boot successfully 3. check DRAM size: 8GB Change-Id: I16449591ec576b1c613a5dad511bafac2bb46f04 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-24mb/google/volteer: Update settings for FPMCU on HalvorJohn Su
Configure gpio settings for FPMCU on Halvor. BUG=b:153680359 TEST=After flash FP MCU FW, during bootup we see spi id spi-PRP0001:01 in dmesg. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5503cfe0fb9933e98ed01afeef8cad1345593ac6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44575 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/volteer/var/halvor: Correct USB device tree settingEric Lai
Halvor uses TBT 0/1/2 for USB type C. We doesn't use PCIE/USB3 port therefore disable PCIE/USB3 ports and enable TBT 2. Follow volteer to set USB2 OC_SKIP. BUG=b:165175296 BRANCH=none TEST=Check all USB ports USB2 and USB3 both functional Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifb844ce475f3d58f0c95be0f172fc49edb4cd5fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/44649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-24mb/google/dedede/var/magolor: Add device settingsRen Kuo
Add the configuration in device tree: 1. Add HDA,speaker codec and speaker amp setting 2. Add Elan and Goodix touchscreen setting 3. Add user facing camera usb setting 4 Add Synaptics and Elan Touchpad setting 5. Add WiFi configuration BUG=None BRANCH=None TEST=build magolor firmware Change-Id: Ifc562b4a05c8955d2aec105f2f429f926ad1e702 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44633 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_tableCaveh Jalali
GPP_D16 is routed to the main power enable pin on several PCIe SD card controllers on SD daughterboards. We should enable the power to these chips as early as possible so they can participate in PCIe enumeration. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-24mb/google/dedede/variants/drawcia: add charger input current throttlingSumeet R Pawnikar
Add charger input current throttling for drawcia system BUG=None BRANCH=None TEST=Built and tested on drawcia system Change-Id: I34fdc23fcd84b5c27c2bada769f7a9049c2a56a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-24mb/google/zork: Add GPIO_144 in touchscreen power on/off sequenceKane Chen
Add GPIO_144 setting to fix touchscreen function not work. 1. Modify reset pin to stop gpio delay to 200ms. 2. Reset GPIO off delay set to 1ms. 3. Add GPIO_144 as stop GPIO. 4. Stop GPIO off delay set to 1ms. 5. Set disable_gpio_export_in_crs = 1. BUG=b:160126287 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I25299861b91cb7b76e512fad743b80221e6ffb4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24mb/google/zork: Fix VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS for WoomaxKane Chen
PROTO stage board version =0. EVT stage board version =1. Modify "VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS" from 2 to 1 for Woomax EVT configuration. BUG=b:165887084 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I894049298bc0313df4fe0a527c55f53ffe56dc8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-23mb/google/zork: disable non-GPU HD Audio deviceFelix Held
The zork devices use the ACP (audio co-processor) and the I2S interface for audio and not the HDA (HD audio) device and interface. BUG=b:158535201,b:162302028 BRANCH=zork TEST=Equivalent change on Mandolin disabled the non-GPU HDA device with the corresponding FSP change applied. Change-Id: I6c7de881cff8398fe416151fab219142d4fc904a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-23soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-22mb/google/puff: Select cse_board_reset() strong symbolEdward O'Callaghan
Since Puff uses CSE Lite SKU that supports in-field CSME updates an additional reset is triggered when jmp from RO to RW during boot. However this reset is not detected by the cr50 running older firmware because the strapping configuration for EFS2 uses PLT_RST_L to assert to cr50 that a AP reset occured. The older cr50 firmware version of 0.0.22 only monitors AP resets via SYS_RESET_L and hence never detects the reset. To mitigate the issue above a modified reset sequence is required to be performed to signal the reset occured and hence a board-specific cse_board_reset() strong symbol is provided to modify the flow accordingly. V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common implementation instead of a local variant in mainboard.c BUG=b:162290856 BRANCH=puff TEST=none Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44454 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-22mb/google/dedede: Enable CSE Board Reset OverrideKarthikeyan Ramasubramanian
This will ensure that the cold reset is performed when CSE Lite jumps from RO to RW. BUG=b:162386991 TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP. Change-Id: I46a390c71e380328cd7fe70214df09553b2db75c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-21mb/google/zork/var/ezkinil: Fix stylus GPIO to enable suspendJosie Nordrum
Make GPIO_4 and GPIO_5 PAD_NC in ezkinil/gpio.c. None of the Ezkinil SKUs use internal stylus and hence pen pads are configured as NC. BUG=b:164892883, b:165342107 TEST=Verified taht pen detect GPIO does not cause spurious wakes. BRANCH=None Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I7557575cf8b8e0f849e05bda1d69acf61e91a157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44629 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21mb/google/zork: provide full range backlight settings to kernelAaron Durbin
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:163583825 Change-Id: I3c337fad38e668488800f4d6bc583a82a93659d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-21mb/google/dedede: Enable IPU for Wdoo and Wdee variantsMaulik V Vaghela
IPU is required to be enabled for platform supporting MIPI camera. IPU is by default disabled in devicetree for all variants. Enable IPU for Waddledoo and Waddledee supporting MIPI camera. BUG=None BRANCH=None TEST=IPU is enabled for platforms and enumerates in lspci. Change-Id: Ia3cf06d78be4301c68bfa8b1118ddff231d24a66 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44271 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-21mb/google/asurada: Fixup BOOT_DEVICE_SPI_FLASH_BUS default valueCK Hu
On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. The number here should be a virtual value as (SPI_BUS_NUMBER + 1). Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ibc269201a34968c8400d2235e8da2ecd88114975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-20src/mainboard: Escape variable expansion in KconfigPatrick Georgi
Kconfig 5.8 interprets $(...) itself using environment variables, which generally means that they expand to the empty string. \$(...) works with both our current and new Kconfig with the desired behavior (to pass it through unmodified). Change-Id: I726567eeb61d2035560152677d2b4548c1472be9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44584 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19mb/google/zork/baseboard: Remove unused referenceMatt Papageorge
Remove references to clk_pm_support which is currently ignored by Picasso AGESA FSP. BUG=b:161218965,b:162423378 TEST=Build test Trembyle and Dali, boot to ChromeOS 5 times each Change-Id: Ic5d6abc56821863b68e45c11763f00d2b6410983 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44556 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19mb/google/volteer: Implement weak function `cse_board_reset`Tim Wawrzynczak
Since Volteer also uses the CSE Lite SKU and the cr50, it is subject to a problem where old cr50 FW will not be able to properly detect an SoC reset, so the reset on cold boots caused by the CSE Lite RO->RW jump should instead get an assist from the EC, which can perform a full cold reset. BUG=b:162977697 TEST=Verify EC performs the cold reset Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie8ae21c203da218459d5fd30a23be23520ed0598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-19mb/google/volteer: Update settings for trackpad on HalvorJohn Su
Configure gpio settings for trackpad. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I525ba688f71b7a1893bcb64c77e02c8e2506d7b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44524 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19mb/google/zork: remove unused asl files for dirinbozKevin Chiu
BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: I713ac3a47c2d47035affb32e6c604b9af23aa90e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-19mb/google/zork: Adjust Dirinboz I2C valuesKevin Chiu
BUG=b:164757545 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully 3. measure i2c freq by scope is close to 400kHz Change-Id: Icb27ff8a4960caaebc542ee4e507f1611da5a77e Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-18mb/google/zork: Clean up bt reset_gpio removalRob Barnes
Clean up of bt reset_gpio removal function. TEST=Boot and observe log showing bt reset_gpio was removed BUG=b:157580724 - Add reset_gpio for Bluetooth Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1d40ad16dd3c624d4be89d9eea1835cc4e72c03d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44273 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpdJohn Zhao
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Volteer EVT board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/44501 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18mb/google/dedede: Fix S3 wake using trackpadMeera Ravindranath
Configure TRACKPAD_INT_ODL pad reset config to DEEP and map PMC_GPE_DW to PMC_GPP values. TEST=System should wake from S3 via trackpad Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18src: Remove unused 'include <stddef.h>Elyes HAOUAS
Change-Id: Iae1e875b466f8a195653d897efa1b297c61ad0a5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41912 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/google/volteer: Make devicetree default as Aux Orientation retimer controlledBrandon Breitenstein
With new board designs being introduced it does not make sense for the default devicetree setting to be retimer disabled on port 0 for Aux Orientation. Change the default to be Aux Orintation retimer controlled on all ports and move the SOC controlled overrides to the corresponding overridetree files. BUG=NONE BRANCH=NONE TEST=Built image for delbin and verified that port 0 flip is working. Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2020-08-17mb/google/zork: Switch to normal read mode for EM100Furquan Shaikh
This change sets the EFS config for SPI read mode to normal read mode when using em100. With this, the boot is stable again without any random hangs in PSP. BUG=b:164429022 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4cd3673dcc44a61905719a57f734df2fb9f4e6e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-17mb/google/dedede/var/magolor: Generate SPD ID for supported partsRen Kuo
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR And also remove the deprecated by cl#43989 https://review.coreboot.org/c/coreboot/+/43989 BUG=None TEST=Build the magolor board Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I3348b7fbeff038b85e7d3c9137517e05a35bf3dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44408 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/google/zork: adjust i2c2 data hold time for TPKevin Chiu
current setting got 0.278us which is less than the min 0.3us. increase i2c2 data hold time for TP. BUG=b:163613330 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. data hold time measured by scope: 0.3805us Change-Id: I2d564983383c17ed43cc5cc5aaff0fcd67ce6928 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17mb/google/volteer: Define stop_gpio for goodix touch screenCaveh Jalali
This applies to the goodix touch screen on both the volteer and volteer2 variants: Define GPP_E3 as the stop_gpio for the touch screen "Report_Switch" signal. Goodix defines a 1ms (minimum) delay after stop off. In addition, no longer drive this GPIO high by default as it is now controlled by the kernel through ACPI. BUG=b:153705232 TEST=touch screen still functional on volteer; confirmed timings with scope (VDD, RESET, REPORT_SWITCH) Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-17mb/google/dedede: Update the SLP_Sx assertion widths and PwrCycDurV Sowmya
This patch updates the SLP_Sx assertion width and power cycle duration for the dedede platforms. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159104150 TEST=Verified that the power cycle duration is ~1.2s with global reset on waddledoo. Change-Id: I7079cbd564288b5d5b69e07661434439365063d3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-15mb: remove unnecessary FADT flag devicetree entries for PicassoFelix Held
Those flags already get unconditionally set in soc/amd/picasso/acpi.c. Change-Id: I978c7d67480499d92c193d5bb87bc876211187db Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-14mb/google/volteer: Only enable TBT root ports if USB4 is supportedBrandon Breitenstein
TBT ports should be disabled if the DB is a USB3 DB. It is assumed if the DB doesn't support USB4 the platform as a whole should only be USB3 capable and TBT functionality on both ports should not be enabled. BUG=NONE BRANCH=NONE TEST=Built coreboot and verified that TBT was disabled on platform with USB3 DB and enabled on platform with USB4/TBT DB Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-14mb/google/dedede: Add a board specific resetKarthikeyan Ramasubramanian
When CSE Lite jumps from RO to RW, global reset is initiated. When AP is reset as part of global reset, TPM initialization fails. This is because AP reset is not detected by TPM hosting an older firmware version. Request Embedded Controller (EC) to perform AP reset so that TPM can detect that event. BUG=b:162290856, b:162386991 TEST=Ensure that the device boots to OS with the board-specific reset sequence when CSE Lite jumps from RO to RW with an older and newer Cr50 firmware. Cq-Depend: chromium:2337430 Change-Id: Ib1f7271130e0b4b68c7f0917ecc4eadba1486206 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-14mb/google/octopus/variants/casta: Disable xHCI compliance modeSeunghwan Kim
Disable xHCI compliance mode to prevent SS hub detection issue. BRANCH=firmware-octopus-11297.B BUG=none TEST=built Change-Id: I7a9bbc92565e752a8f8f4689519c100594596701 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44438 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-14mb/google/octopus: Set default value of ModPhyIfValue parameterSeunghwan Kim
Set default value of ModPhyIfValue parameter in FSPS_UPD. Without this setting, it will be set to '0' and system may not detect USB 3.0 device. BUG=b:163382089 BRANCH=firmware-octopus-11297.B TEST=Built Change-Id: Ide3d1637f99dba28251102f771b6ce370cc5d8e4 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-13mb/google/zork: Switch to using FW_CONFIG instead of SKU_IDBhanu Prakash Maiya
Currently sku_id is used to enable/disable eMMC as boot media on Dalboz. This patch will check eMMC bit in firmware configuration table to enable/disable eMMC. On Dalboz Proto and EVT devices with eMMC, there was an issue found after SMT. This patch checks for board_version instead of SKU_ID to configure eMMC in HS200. Configure HDMI based on daughterboard_id in FW_CONFIG. BRANCH=none BUG=b:152817444 TEST=Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: Ifa2a49a754d85fb6269f788c970bd9da58af1dad Reviewed-on: https://review.coreboot.org/c/coreboot/+/44421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-13mb/google/zork: Use FW_CONFIG to enable/disable eMMC on EzkinilBhanu Prakash Maiya
Currently SKU_ID is used to enable/disable eMMC as boot media on Ezkinil. This patch will check eMMC bit in firmware configuration table to enable/disable eMMC. BRANCH=none BUG=b:162344105 TEST=Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: I62318cf71ec70790f2d9e787febd1e0b787741fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/44423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-13mb/google/zork: Add helper function to read DB ID bits in FW_CONFIGBhanu Prakash Maiya
Add helper function variant_get_daughterboard_id() to read daughterboard id bits (0-3) in firmware configuration table in CBI. BRANCH=none BUG=b:162344105,b:152817444 TEST=Check if daughterboard id bits (0-3) can be read from FW_CONFIG. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: Ia3c882439bfbe6da28be2df0ec0c976d5c142677 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44424 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13mb/google/zork: Remove validity checks for FW_CONFIG in CBIBhanu Prakash Maiya
After confirming that all zork variants and phases have valid FW_CONFIG value in CBI, this patch is dropping FW_CONFIG validity checks like VARIANT_HAS_FW_CONFIG and VARIANT_BOARD_VER_FW_CONFIG_VALID in Kconfig and will also remove associated helper functions. BRANCH=none BUG=b:162344105,b:152817444 TEST=Check if FW_CONFIG bits can be read in coreboot and FW_CONIFG helper function do not return 0 if board has a valid FW_CONFIG in CBI. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: I633dc7c500ef8759f3fffb0db6b76d96257c3c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-13mb/google/volteer/var/halvor: Update dq/dqs mappingsFrank Wu
Update dq/dqs mappings based on halvor schematics. BUG=b:162892573 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Then boot Halvor successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id4ffcbd4f015afe6507ed2b1d562519c5b240409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 09:29:25 +0000