summaryrefslogtreecommitdiff
path: root/src/mainboard/google
AgeCommit message (Collapse)Author
2019-09-11src: Remove unneeded include <arch/interrupt.h>Elyes HAOUAS
Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-11mb/google/hatch: Create dratini variantWisley Chen
Create dratini variant BUG=b:140610519 TEST=emerge-hatch coreboot, and boot into chromeos on proto board Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35285 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11mb/google/drallion: enable Elan and Melfas touch panelEric Lai
Drallion uses the same touch panel as Sarien. Copy the deivce from Sarien. BUG=b:140415892,b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35305 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10mb/google/kukui: Enable MT8183_DRAM_EMCPHuayang Duan
MT8183_DRAM_EMCP is enabled for devices using eMCP to run at a high DRAM frequency (e.g., 3600Mbps). BUG=b:80501386 BRANCH=none TEST=Memory test passes on EMCP platform Change-Id: Icf875427347418f796cbf193070bf047844d2267 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34433 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10mb/google/poppy/variant/nocturne: add EC_SYNC_GPIONick Vaccaro
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO.. - change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low - add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel. Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-10mb/google/hatch/variants/helios: Modify FPU power on sequenceFrank_Chu
pull in the FPU VDDIO turn on to fix the power leakage problem on FPU VDDIO and FPU CS during power on sequence. BUG=b:138638571 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I3f6bf3676922e987c2e282b697a2333e2d90289e Reviewed-on: https://review.coreboot.org/c/coreboot/+/34858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-10mb/google/octopus: Add a new sku for meepWisley Chen
Add a new sku4 for meep: sku4: Stylus + no rear camera BUG=b:140360096 TEST=emerge-octopus coreboot Change-Id: Icde7f032c0acf7562b5d5f2c6a8b0c2de91c45b2 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-09-10mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clockPeichao Wang
Tune I2C bus 1, 2 and 3 clock and make them meet spec. BUG=b:140665478 TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock frequency less than 400KHz Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35298 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectivelyPeichao Wang
1. SKU1 for eMMC 2. SKU2 for SSD BUG=b:140008849, b:140573677 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09lib/spd_bin: Extend DDR4 spd informationEric Lai
From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-09mb/google/drallion: modify USB settingEric Lai
Based on HW schematic to modify USB setting. Drallion has two type C on left and two type A on right. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-06mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2Frank_Chu
Applying first tuned DPTF parameters and TDP PL1/PL2 values for helios. BUG=b:138752455 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-09-05mb/google/octopus: Set sar file name for meep skuWisley Chen
Set meep sar file name by sku number Cq-Depend: chromium:1768380 BUG=b:138261454, b:118782854 BRANCH=octopus TEST=emerge-octopus coreboot, and check wifi_sar-meep.hex Change-Id: I25aa3080392ce277e537c973088dde569246630e Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-05mb/google/drallion: modify PCIE settingEric Lai
Based on HW schematic to modify PCIE setting. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-05mb/google/octopus: Load custom SAR values by SKU ID for BloogTony Huang
Use sku-id to load the SAR values for Bloog device. BUG=b:138180187 BRANCH=octopus TEST=build and verify load Bloog SAR by sku-id Cq-Depend: chromium:1771477 Change-Id: Id0bc2609fd1c4eaeb380f8f1532ab30d34e2aeb3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-04mb/google/kahlee/treeya: Update the memory timing table for Treeya to the 2T ↵Peichao Wang
table Rename the table from Liara specific to simply specifying that it's using 2T command rate BUG=139841929 TEST=build and do stress test Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-04mb/google/kahlee/treeya: override sku_id() functionPeichao Wang
override 'uint32_t sku_id(void)' so that lib_sysinfo.sku_id get a correct value in depthcharge BUG=b:140010592 BRANCH=none TEST=boot treeya board, in depthcharge stage, lib_sysinfo.sku_id print correct value. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I631f62021e8104a69a43667a811c9c23e3105596 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Magf - <magf@bitland.corp-partner.google.com> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-04mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2David Wu
Add TEMP_SENSOR_3 to DPTF, Update DPTF parameters and TDP PL1/PL2 values Cq-Depend: chromium:1751304 BUG=b:140127035 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-ec chromeos-bootimage Change-Id: I1817e277f4641db6bedc8b640b1dc5d57502d5dd Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-09-03mb/google/hatch/var/kindred: Update DRAM IDs for 8G and 16G 3200David Wu
Update DRAM IDs to support 8G and 16G 3200 spds BUG=b:132920013 b:131132486 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: I8e55b5e24ee2cefe90472a331e829b073bf0f92a Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-02mb/google/drallion: add memory sku idEric Lai
Drallion will use soldered down memory and use GPP_F12 to GPP_F16 indicates mem_id. BUG=b:139397313 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a Reviewed-on: https://review.coreboot.org/c/coreboot/+/35133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-02mb/google/drallion: Enable HDA for drallion platformAamir Bohra
Enable PchHdaIDispCodecDisconnect and PchHdaAudioLinkHda for drallion variants. This is needed with FSP 1263. Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: I13d3dd832c6fbdc2aad5ba578695edb8470806e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-02mb/google/hatch/var/helios: Increase touchscreen reset delay to 120msPhilip Chen
As per GT7375P programming guide rev0.4, we want to enforce a delay of 120ms after the reset is completed, before HID_I2C starts. BUG=b:140276418 Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/35158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-30mb/google/octopus/variants/garg: update new SKUKevin Chiu
For Garg EVT build, add new SKU ID below: SKU4 LTE DB, touch: SKU ID - 18 SKU5,6 Convertible, 2A2C, Touch, Stylus, rear camera: SKU ID - 37 BUG=b:134854577 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Iea1d17efb9a5f274f8eefb2aaa683e75ab5de7d2 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-08-30mb/google/kahlee/variants/careena: override DRAM SPD tableKevin Chiu
override DRAM SPD and add new 4 DRAM: Samsung (TH) K4AAG165WA-BCTD Hynix (TG) H5ANAG6NCMR-XNC Micron (TF) MT40A1G16RC-062E:B Samsung (TH) K4AAG165WA-BCWE BUG=b:139912383 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage extract spd.bin and confirm 4 new SPD was added. Change-Id: Ie1b2c1bae5ffe9f3a6a6560348f6e1b117ffd457 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-30google/buddy: adjust CID for realtek audio codecMatt DeVillier
Adjust CID to allow for Windows driver to attach without breaking functionality under Linux. Same change made as to google/cyan (which uses same Realtek RT5650 codec) in commit 607d72b. Test: build/boot Windowns 10 on google/buddy, observe audio drivers correctly attached to codec and Intel SST devices. Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30mb/google/drallion: change servo board debug to UART 0Eric Lai
Drallion will change debug port UART from 2 to 0. Followed HW schematic to modify it. BUG=b:139095062 BRANCH=N/A TEST=Build without error Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-30mb/google/hatch: Add settings for noise mitgationDtrain Hsu
Enable acoustic noise mitgation for hatch platform, the slow slew rates are fast time dived by 8 and disable Fast PKG C State Ramp(IA, GT, SA). BUG=b:131779678 TEST=waveform test and reduce the noise level. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-30mb/google/hatch: Add 16G 3200 generic SPD fileShelley Chen
BUG=b:139792883 BRANCH=None TEST=None Change-Id: I22974b015a40fb7ae592e182cf5da83a8252c031 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-29arch/arm: Make ARM stages select ARCH_ARMArthur Heymans
This removes the need to select ARCH_ARM in SOC Kconfig Also don't define the default as this result in spurious lines in the .config. Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31313 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29mb/google/drallion: Update memory mapBernardo Perez Priego
This will enable to optionally inject ISH binaries into coreboot. BUG:b:139820063 TEST='compile successfully' Change-Id: I38659460726a3f647cda3bc3efd442f18aea24f0 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-29mb/google/drallion: Correct drallion HWID and add HWID for variantsMathew King
The current HWID for drallion is reported as invalid by chrome, generate new valid HWID with the following command and taking last 4 digits. `printf "%d\n" 0x$(crc32 <(echo -n '$1'))` BUG=b:140013681 Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-28google/rambi,intel/baytrail: Simplified romstage flowKyösti Mälkki
Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28mb/google/hatch/variants: Increase touchscreen reset delay to 120msSumeet Pawnikar
During boot sequence sometime touchscreen reset keeps failing. Also, kernel dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message. This adds around 4 more seconds to the boot sequence. Setting the appropriate delay of 120ms between enable and reset for Goodix Touchscreen helps to synchronize and address this failure. This value is 120 ms as per Goodix Spec. BUG=b:138413748 BRANCH=None TEST=Built and tested on Hatch system Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28google/leon: Add DRIVERS_I2C_RTD2132Kyösti Mälkki
This is LVDS bridge, I assume this was lost while upstreaming or converting boards to variants. Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-08-28mb/google/hatch: Enable Override DLLs for KindredJamie Chen
Enable SOC_INTEL_COMMON_MMC_OVERRIDE for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I390d237b9119ae42f4b0bb802bf9857552af78bf Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-28mb/google/hatch: Override DLL values for KindredJamie Chen
New emmc DLL values for Kindred BUG=b:136784418 BRANCH=none TEST=Boot to OS 100 times on Kindred proto 1 board. Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35041 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28mb/google/drallion: remove GBE fileEric Lai
Drallion doesn't have on board LAN, remove GBE bin file config. BUG=b:139906731 TEST=emerge-drallion coreboot chromeos-bootimage and check image-drallion.bin not include GBE region Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-28mb/google/drallion: add dummy SPD fileEric Lai
Drallion will use soldered down memory. Add dummy spd file. BUG=b:139397313 BRANCH=N/A TEST=Build and check cbfs has the dummy spd.bin Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28mb/google/poppy/variant/nami: add sku ids of bard/ekkoRen Kuo
add sku ids of bard/ekko BUG=b:139886622 TEST=emerge-nami coreboot Change-Id: Iabc3d587c3839e4a3121cea8504c50e2dc4f9699 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35115 Reviewed-by: Vincent Wang <vwang@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26Split MAYBE_STATIC to _BSS and _NONZERO variantsKyösti Mälkki
These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26google/kukui: Enable CHROMEOS_USE_EC_WATCHDOG_FLAGYu-Ping Wu
Kukui AP doesn't remember if the last AP reset was due to AP watchdog. We need to enable CHROMEOS_USE_EC_WATCHDOG_FLAG so that it will query the reset reason from EC. BUG=b:109900671,b:118654976 BRANCH=none TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog' 2. wait for watchdog reset 3. check 'mosys eventlog list | grep watchdog' Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-26google/link: fix detection of dimm on channel 1Matt DeVillier
Changes to the sandybridge memory init code (both MRC and native) now require SPD data on all populated channels in order for dimms to be detected properly, so copy spd_data[0] to spd_data[2], as LINK always has 2 channels of memory down. Test: boot google/link, observe onboard RAM correctly detected on both channels Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-08-24mb/google/octopus: Re-assign sku number for vortininjaWisley Chen
Re-assign sku number for vortininja. BuG=b:138177049 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I3166a635151fcc7b2e3c0122fa05925cfa5df7d0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-23mb/google/hatch/var/kindred:: Add enable signal for touch screenPhilip Chen
In the next board version, we will use GPP_D9 as enable control for touch screen. BUG=b:137133946 TEST=build Change-Id: I213d0878bfca1ce4059ec0393f59d8e79e1b274c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23mb/google/hatch/variants/kindred: Remove unused devicesPhilip Chen
sx9310 and FPMCU are not used in Kindred. BUG=none TEST=build Change-Id: Ied09d4bdb899d991131a75d7c848ff8637022f53 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23mb/google/rambi: update GPIO, RAM config for clapperMatt DeVillier
When upstreamed, GPIO and RAM config for clapper variant was taken from an older branch, leading some boards to fail to boot. Update based on chromium branch firmware-clapper-5216.199.B, commit 362d845 [baytrail: implement baytrail technical advisory 556192] Change-Id: I099ee2cd0833e4b9ab093663c4549c79ec044127 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-23Revert "mb/google/octopus: Disable WLAN prior the entry of S5"Kane Chen
This reverts commit 38dbd6892080c93ccd24fbfa46ed5d9bdb7d9e99. Reason for revert: ODM helped to verify w/ BT runtime suspend disabled + revert this change And issue is gone. so I revert this change see the test result in https://partnerissuetracker.corp.google.com/issues/136039607#comment32 Change-Id: I248e9613cc39247a2bb88270c234c7d36d0ff60f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-23mb/google/drallion: Add two variants - arcada_cml & sarien_cmlThejaswani Putta
These variants are to support the sarien and arcada boards with CML SOC, the drallion variant will be used to support the upcoming drallion board. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I766bdccb6f8b6924d6ae1abbe57035f4ff1f6f17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-23mb/google/kukui: Add panel for KodamaPeichao Wang
Declare the following panel for Kodama: - AUO B101UAN08.3 BUG=b:139699622 TEST=builds Kodama image and working properly Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I3f688ffd0ece6afac08d353ab5a6cf1cf876b32f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35001 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 01:00:08 +0000