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2019-03-25vboot: remove VBOOT_EC_SLOW_UPDATE Kconfig optionJoel Kitching
This option has been relocated to depthcharge: https://crrev.com/c/1524806 BUG=b:124141368, b:124192753 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild CQ-DEPEND=CL:1524806 BRANCH=none Change-Id: Ib4a83af2ba143577a064fc0d72c9bc318db56adc Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31909 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-25gale: add dev switch back as physical presence GPIOJoel Kitching
gale has a button which is essentially used as a "physical presence" button. Its only use is to emulate ^D or ^U on boot when the button is pressed. (See depthcharge src/board/gale/board.c) Previously (and currently in CrOS firmware branch) this GPIO was defined as the physical developer switch, and read as such in depthcharge. It was removed in cleanup patch CB:18980. Add the GPIO back as physical presence ("presence"), which will be read by depthcharge in CL:1532492. BUG=b:124141368, b:124192753, chromium:942901 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic144f839b7f9933d573db8f84c4bf5905eea96f6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-25mainboard/google/sarien: skip tpm check when !verstageJett Rink
The TPM driver isn't loaded in other stages but verstage so when we try to communicate with the TPM it fails. We don't need to communicate with it anyway since the TPM won't continue to tell us that recovery was requested, only the first query responds with the recovery request. BRANCH=none BUG=b:129150074,b:123360379 TEST=1)boot arcada without recovery and notice that the "tpm transaction failed" log lines are no longer present. 2) boot into recovery using the ESC refresh power key combination and verify that the recovery reason was "recovery button pressed" Change-Id: I13284483d069ed50b0d16b36d0120d006485f7f4 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-22mb/google/poppy/variants/atlas: DPTF tuning v2Puthikorn Voravootivat
We have more test data now so update the DPTF accordingly. * Change passive temp to 50/57/55/52 C * Change critical temp to 75C * All interval to 20 secs BUG=b:113101335 TEST=temp/perf looks better in thermal chamber test. Change-Id: I872c3f1875d0cbac148c44c449954e6871c9d0b0 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22mb/google/hatch: Enable FP MCUShelley Chen
AP communicates with FP MCU through gspi1. BUG=b:126455006 BRANCH=None TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg FP MCU fw is not ready yet, so not much testing to be done yet. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32017 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-22mb/google/hatch: Add overridetree to hatch variantShelley Chen
Add serialio settings to hatch. Only applies to CML. BUG=b:128347800 BRANCH=None TEST=abuild Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32003 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-22mb/google/octopus: Add keyboard backlight support for bloogTony Huang
Bloog supports keyboard backlight feature, so enable the ASL code. BUG=b:127736039 BRANCH=octopus TEST=Build and boot bloog, verify that the string 'KBLT' is in the DSDT. Change-Id: Iba66aade090816ea2376cae4baf4aae019cc97f4 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-03-22arch/mips: Fix <arch/mmio.h> prototypesKyösti Mälkki
These signatures need to be consistent across different architectures. Change-Id: Ide8502ee8cda8995828c77fe1674d8ba6f3aa15f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-22mb/google/hatch: Add SX9310 SAR0 sensorEvan Green
Add SAR0, which is an SX9310. The schematics and layout have a second SAR1 sensor provisioned on I2C4, with an interrupt of GPP_A6, but this is not populated. Signed-off-by: Evan Green <evgreen@chromium.org> BUG=b:128540461 BRANCH=none TEST=Boot kernel with sx9310 driver, see it come up happily Change-Id: I63943cc7da5ff56f6ef6dcbd99bb8f8f031e8bf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-22mb/google/hatch: Enable HUNG_TASK wake interruptEvan Green
Enable the HUNG_TASK as a wakeup host event, as it's used by S0ix failure detection to wake the system back up if a suspend to S0ix never asserted S0_SLP#. BUG=b:123716513 BRANCH=None TEST=Test S0ix on Hatch with appropriate EC and kernel changes. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I447211892df210af97e8df0380bab032b14cbee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32004 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21grunt: Mark RW_LEGACY as CBFSMathew King
Depthcharge is changing how the RW_LEGACY CBFS is handled for alternate bootloaders, see https://crrev.com/c/1528550 and https://crrev.com/c/1530303. This means that RW_LEGACY must be marked as CBFS in the fmap in order to work. All boards except for kahlee(grunt) have CBFS marked. BUG=b:128703316 TEST=Build and ran on grunt along with chromium patches on grunt and was able to list alternate bootloader with ctrl+l BRANCH=none Change-Id: I843d565a9503d27e666a34e59aba263ec490c81f Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32019 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21vboot: remove VBOOT_EC_EFS Kconfig optionJoel Kitching
This option has been relocated to depthcharge: https://crrev.com/c/1523248 BUG=b:124141368, b:124192753, chromium:943511 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild CQ-DEPEND=CL:1523248, CL:1525647 BRANCH=none Change-Id: I8b3740c8301f9a193f4fce2c6492d9382730faa1 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31897 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI portsKrishna Prasad Bhat
Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all DDI ports are enabled and hence configures the HPD and CLK for DDI ports. This patch initializes only the required UPDs to enable display ports. BUG=b:123907904 TEST=DP devices working correctly. Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-21mb/*/chromeos.c: Be explicit about code for ramstageKyösti Mälkki
Motivation is to reduce use of !__PRE_RAM__, it does not mean ENV_RAMSTAGE but we also exclude ENV_SMM with the change. Change-Id: I1f96bb8c055a3da63274e1ab7f7d4bc70867cbf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-21mb/google/sarien: Add SKU for boards with signed ECDuncan Laurie
To support both boards with the same firmware add a SKU for each variant that is used to include the proper EC firmware image to match what the EC is expecting. BUG=b:119490232 TEST=tested by faking the EC response to ensure that the OS and firmware update tools are able to determine the correct model based on the value returned by the EC. Change-Id: Iaa677975e0bccbee5ec8a39821fe1637f08270fa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-20google/mistral: Implement board resetsanthosh hassan
Implement reset using PSHOLD. Change-Id: I472bf73cc7b227187b284a3730ec5dea5373695c Signed-off-by: Santhosh Hassan <sahassan@google.com> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-20mistral: qcs405: copy calibration data to CBMEMNitheesh Sekar
This patch adds support to copy the wifi calibration data to CBMEM so that the depthcharge can use it to populate the data into wifi dt node. Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-19mb/google/hatch: Log EC events during S0ix resumeV Sowmya
This change adds support for logging EC events during S0ix resume. BUG=b:124131938 BRANCH=none TEST=Verified that the wake events are logged during the S0ix resume: 4 | 2019-03-05 07:55:27 | System Reset 5 | 2019-03-05 07:55:27 | Chrome OS Developer Mode 6 | 2019-03-05 07:56:54 | S0ix Enter 7 | 2019-03-05 07:57:09 | S0ix Exit 8 | 2019-03-05 07:57:09 | Wake Source | Power Button | 0 9 | 2019-03-05 07:57:09 | EC Event | Power Button Change-Id: I624f94c29bc66dbf4d9e1fec573d259985260ed3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-19src: Drop unused 'include <cbfs.h>'Elyes HAOUAS
Change-Id: If5c5ebacd103d7e1f09585cc4c52753b11ce84d0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-18mb/google/hatch: Set hatch to use SOC_INTEL_COMETLAKEShelley Chen
Move these configs to Kconfig.name as well. BUG=b:127310803 BRANCH=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I793363740fa0730a1e9e1aa7a9fa82d2789334b4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-18mainboard/google/mistral: Add support for MistralNitheesh Sekar
Adding a new board variant 'Mistral' based on qcs405 soc. TEST=build Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18soc/intel/common: Update ESPI disable optionDuncan Laurie
Update the Kconfig option for disabling ESPI SMI source to disable it entirely, not just when ACPI mode is disabled. For the situations where this is needed (just the sarien board) it is better to completely stop the EC from sending any SMI events as no actions are taken. Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18mb/google/sarien: Enable BT RkfillLijian Zhao
Add bluetooth Rfkill function to recover the Bluetooth controller in cases where itself has entered a bad state and needs to be recovered. Bug=b:123342945 TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under Bluetooth devices with GPIO in. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibbe67887227af42b6c040deade7bf5da4ce3227f Reviewed-on: https://review.coreboot.org/c/coreboot/+/31765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18mainboard/google/kahlee: Don't use AMD's secure OSMartin Roth
Disable the use of AMD's Secure OS through the Kconfig option. BUG=chromium:903833 TEST=Build google/aleena, verify types 02, 0c, 0d are removed from PSP directory table Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iabb0632eef88170dde45dea2e2e15b54b3a06f7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/31890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-03-16x86/smbios: Untangle system and board tablesNico Huber
We were used to set the same values in the system and board tables. We'll keep the mainboard values as defaults for the system tables, so nothing changes unless somebody overrides the system table hooks. Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-16src: Drop unused '#include <halt.h>'Elyes HAOUAS
Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-15mb/google/hatch: Enable TBMC deviceDtrain Hsu
This change enables tablet mode ACPI device for all hatch boards. BUG=b:125355874 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I4d3818497172828d750b34fe91cbb6cc65e69fc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-14mb/google/kahlee/aleena: Add EC_ENABLE_TBMC_DEVICEEdward Hill
Enable ACPI TBMC notification on tablet mode change to support convertible Aleena devices. BUG=b:124132058 BRANCH=grunt TEST=evtest shows tablet mode events Change-Id: Iaf8ef031d4660f0791b5f664880437e6dfa58dc8 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-14mb/google/arcada: Update USB2 port6 AFE settingLijian Zhao
Accoriding to 574354, we need to tune each port to pass eye diagram other than just use recommanded setting as they are base guidence only. Bug=b:124407280 TEST=Build and boot up on arcada board. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I587695809b368edd33852c4241de097ca31e9d66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31632 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14mb/google/hatch: Define GPP_C13 as EC_SYNC_IRQPhilip Chen
BUG=b:125933998 CQ-DEPEND=CL:1510513 BRANCH=None TEST=manually verify on hatch, chromeos-ec interrupt count increases Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: I1dd38ca5aed1e0ddecb4738910cbfa92de33d315 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31814 Reviewed-by: Enrico Granata <egranata@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14mb/google/hatch: fix RCompResistor[0] valueShelley Chen
From doc#573387 CML System Memory DQ DQS Rcomp Mapping Information User Guide, RCompResistor[0] should be 121. BUG=b:122959294 BRANCH=None TEST=emerge coreboot and make sure boots up Change-Id: If69e7fb41e79d88d21b0e50fb65107a1686d696a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31868 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14mb/google/hatch: Update DRAM IDsShelley Chen
Update Hatch DRAM IDs to use the new DRAM ID assignment for general spds: 0 = 4G 2400 1 = 4G 2666 2 = 8G 2400 3 = 8G 2666 4 = 16G 2400 5 = 16G 2666 BUG=b:122959294 BRANCH=None TEST=emerge coreboot and make sure boots up Change-Id: Ic47737ce37597318bb794b63a47ced2467d8bbb0 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-14mb/google/hatch: Use MEM_CH_SEL to indicate single_channel skuShelley Chen
MEM_CH_SEL is used to indicate whether we are on a single or dual channel device, where MEM_CH_SEL = 1 for single channel skus and MEM_CH_SEL = 0 for dual channel skus. Initialize single_channel field (from GPP_F2), which will in turn initialize MemorySpdPtr pointers in cannonlake soc code. In the first build, we did not use GPP_F2, so we need to add an internal pulldown as those early devices were all dual channel devices. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Also, verify that GPP_F2 is set to 0. Change-Id: I89d022793580be603a93d0b177d73ce968529b5c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-14mb/google/octopus: Create Bloog variantTony Huang
This commit create bloog variant for Octopus. Initial settings are copy from meep. Remove I2C tuning, WACOM digitizer and WEIDA touchscreen. Override GPIO configuration for unused LTE and Pen. BUG=b:127736039 BRANCH=octopus TEST=None Change-Id: I1d04c97cb0622075a25825ba2c835d556c8b0423 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-03-14mb/google/hatch: Query the EC for board versionIvy Jian
The board version is part of EC's EEPROM, select Kconfig items to enable requesting the EC for board version. BUG=b:128385395 TEST=Verified the mainboard version is from EC's EEPROM. Change-Id: I4bc1cac43c6cf73522f3a4bee89cc000a430d996 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31858 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14mb/google/arcada: add Kconfig option to enable WLAN SARCasper Chang
Enable WLAN SAR power table. BUG=b:123552641 TEST=Verified WLAN SAR power table forllows VPD setting Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I882b1c7ed0b1142a84eb338142e1c984df45eeba Reviewed-on: https://review.coreboot.org/c/coreboot/+/31859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-13mb/google/hatch: Provide DRAM part number from EEPROMFurquan Shaikh
This change reads DRAM part number from EEPROM if available and returns it using the SoC callback (mainboard_get_dram_part_number). BUG=b:127609572 TEST=Verify that DRAM part number from EEPROM is added to DMI table 17 (dmidecode -t 17). Change-Id: I6ade6999828b6d67aa78d04199138f195a97ba8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-13src: Drop unused 'include <arch/ioapic.h>'Elyes HAOUAS
Change-Id: I1341f90230f318ac81a4aea24872ff272adad1eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31856 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-12src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS
Use <arch/acpi.h> when appropriate. Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-11mb/google/hatch: Add Hatch_whl boardShelley Chen
Adding Hatch_whl as a variant of hatch. This is a snapshot of the WHL version of hatch so that we can rebuild the bios images for Hatch with WHL SoC. BUG=b:127310803 BRANCH=NONE TEST=./util/abuild/abuild -p none -t google/hatch -x -a make sure HATCH_WHL is built as well. Change-Id: I24510fa226878582a61f1846f0b56a2c65204a92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-11mb/google/hatch: Enable audio supportSathya Prakash M R
Following changes are done to enable audio support on hatch 1. Enable I2C4 device at 400Khz at 1.8V 2. Configure GPIO for HP INT and SPKR_PA_EN 3. Add ACPI entry for RT5682 and MAX98357A 4. Enable I2S0 and I2S1 lines 5. Enable generic max98357a driver in Kconfig BUG=b:123738217 BRANCH=none TEST=Check SSDT table for RT5682 & MAX98357a entry. Verify audio using Sound Open firmware (SOF) Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84 Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-08mb/google/hatch: Create hatch_whl variantShelley Chen
In preparation for the transition of hatch from WHL to CML, we are creating a checkpoint called hatch_whl that we can use for creating firmware compatible with the WHL hatch variant. BUG=b:127310803 BRANCH=NONE TEST=NONE Change-Id: Iecae584ee6feefcf29955a4720e9c24bdc8abe6d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08mb/google/hatch: Initialize all gpiosShelley Chen
BUG=b:123490912 BRANCH=None TEST=flash BIOS and make sure hatch boots up properly Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31724 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07src: Drop unused include <timestamp.h>Elyes HAOUAS
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-07mainboard/google/kahlee: Add additional Micron MT40A512M16TB-062E:J SPD for ↵Kevin Chiu
variants BUG=b:127394249 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage Change-Id: Ibb4beddf186233fd82ec8f3a01bf14d00b1352ff Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31778 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06mb/google/poppy/variants/nami: Use Pantheon VBTJohn Su
Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Change-Id: Icd56905e1e04de6f307393ae23f741b93ff23a4c Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31747 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06mb/google/sarien: add ish firmware_variant field to _DSDJett Rink
We want to publish "arcada_ish.bin" as the fw name for Integrated Sensor Hub (ISH) so the kernel shim loader code can use it to construct the correct path in /lib/firmware/intel for the firmware load process. BUG=b:122722008 TEST=Verify that shim loader CLs use new value when constructing firmware path Change-Id: I6299de82566a3bad8521f8158bb047d5c1ff0cf8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-06Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki
The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 05:06:16 +0000