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The only remaining purpose for get_bus_conf() was to fill in obscure
bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete
enumeration is available in devicetree and PCI configuration space so
discard these arrays.
Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6360
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6359
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Previously MP table contained PCI_INT entries for PCI bus behind bridge
0:14.4 even if said PCI bridge function was disabled.
Remove these as invalid, indeterminate bus number could cause conflicts.
PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2]
were invalid as there is no PCI bridge hardware on device 0:14.0.
Remove these as invalid, indeterminate bus number could cause conflicts.
Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6358
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I3807912b1dc68fae8248a66e37bbe642fb92d3ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6262
Tested-by: build bot (Jenkins)
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Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper
while AMD_INIT_ENV was already handled as part of BiosCallouts.
OEM configuration is supposed to be implemented as part of BiosCallouts,
leaving agesawrapper agnostic of platform details.
TODO: S3 resume for XHCI1.
Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6241
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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Change-Id: I5b3cbc4d25f06a5f916760d4474621abbf826ee4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6355
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Integrated PCI devices in southbridge silicon have static BDFs,
no need to have variables to store the parent bus or an offset
with constant zero.
Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I7f681b40251f49ff717589ed5e7d7e00ee36c7c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6332
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Only ever used as lvalue (except when incrementing) so this global
is unused.
Change-Id: I616721f937eb0bfdb28f356284efd70f99ccd2dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6330
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6308
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: If29a70be4fb56ebb0dbf6d510412cbe2f34480ef
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6291
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Found using coccinelle.
Change-Id: I406de6cfe25d3b471dbb6f98d9c62addae008de3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6195
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Only ever used as lvalue, so no point creating the array.
Change-Id: I6699dfae9377a895e9bc4a52579d00ddcfa60a9f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6277
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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Change-Id: Ib531a54db7df6b49a6218f689dcaab712e9dfb01
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6292
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
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Like many other (but not all) BiosCallouts, StdHeader is also passed
as ConfigPtr argument. Use that instead to make no assumptions of the
real type of FchData as it changes depending of the StdHeader.
Change-Id: Ibdf01d08e63b9e1b8e99ac16abb7f807d37a056e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6240
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: Ib2a015dac82cec8538f8b1a1c2d45b20b05747bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6239
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Martin Roth <gaumless@gmail.com>
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Implement logging just once to have uniform output.
Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6180
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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AGESA correctly uses the enum AGESA_STATUS type whereas boards use a
mess of UINT32 typecasts.
Also no need to shout VOID. We are not that careful on changing
all cases of VOID->void or whitespace issues as these files will
get merged with follow-ups.
Change-Id: I16ccfcc73cda6b917c7ff5fd42ee2cd04e7dc0dd
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6182
Tested-by: build bot (Jenkins)
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Change-Id: I4a4ee99468e5f1dae8412ae565a34290493db726
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6201
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I05d6d22664155ac8478e665733f816776e277c22
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6200
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ie3287cba45bd6f4f8823ce03cd9983707c9ad0de
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6194
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
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Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6143
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Instead of calling get_bus_conf() three times from write_tables()
and executing it once, just make one call before entering write_tables().
Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6133
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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NOTE: The procedure is moved across a collected timestamp
TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted
for in an earlier entry in cbmem -t output.
Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6132
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the
build of romstage also for boards without HAVE_ACPI_RESUME.
These symbols got exposed as the use of preprocessor directives was
reduced.
We expect the linker to do a fair job and optimize away function
bodies that are on unreachable execution paths.
Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6067
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Use one common implementation for all AGESA platforms.
Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6084
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I92f3877b58d9acaa9578337e66107e9cd9f46043
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6110
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I4d8abe3841378e06515e1b3a8f22d78425d08449
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6109
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4525
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Try to 'standardize' the otherwise peculiar method naming to be somewhat
more in-line with other ACPI implementations. This makes it easier to
compare with vendor DSDT dumps for example.
Change-Id: I5ba54f7361796669ac0cab7ff91e7de43b22e846
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5888
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Use the following command to fix all occurences.
$ git grep -l approriate | xargs sed -i 's/approriate/appropriate/g'
Change-Id: I4cbba972bb445c2407ef2e63ffb3068fc948f1c6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5987
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I5df1f0efdef2592b762fe391edaadbca4593e85a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5689
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I9c8f7cc98c65102486e17ec49fa2246211dffc4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5688
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: Ibbb07ef308c7e92a8a8dfe066f5e3866d5f8aee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5687
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I158993bcb654ef27a9fc6b7e9dc3fc955fb740fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5686
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Most of the callouts are not specific to board or even family.
Start new file with default callouts doing nothing and returning
either AGESA_SUCCESS or AGESA_UNSUPPORTED.
Also add callout for returning empty IdsIdData. This feature is
not used and could be easily overriden at board-level at later time.
Change-Id: I65dbcdd80dddc89d47669ebe62c22caa63792f5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5678
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Remove use of global variables uma_memory_base and uma_memory_size
from builds with Intel northbridges, as these variables can be kept
within the chipset or even as stack locals.
Intel platforms have no functional implemenation for option GFXUMA.
If we did implement some choice between external and integrated graphics,
it needs to be named in less obscure fashion.
Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5720
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.
Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Lines with 'select SERIAL_CPU_INIT' where redundant with the
default being yes. Since there is no 'unselect SERIAL_CPU_INIT'
possibility, invert the default and rename option.
This squelches Kconfig warnings about unmet dependencies.
Change-Id: Iae546c56006278489ebae10f2daa627af48abe94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5700
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Following the same reasoning as commit
d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid
.c includes
Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5439
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Overriding global config entries in mainboard directory Kconfig
files often raise unnecessary warnings. Squelch some of those.
Change-Id: Ib5127672ae068670028aa25c8ccb5366277622f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5699
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear
the fields individually.
Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5659
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Implementation of this function is common for all boards in family,
and also across different families.
Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.
Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5570
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Following the reasoning of:
dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c
Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5597
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Dumping the ACPI tables in this way has limited use, is not likely to be
used and is poorly implemented. There are much more sophisticated tools
available on Linux for debugging ACPI as such this code is outside the
scope of coreboots 'bring up the hardware only' philosophy.
A more generic implemention could be done with hexdump() in coreboot
proper following on from this cleanup.
Change-Id: Ifd3bfb76338609d18fcf7158d3c9a6d7c06c8847
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5530
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The PCIE PME pin from the APU is connected to GEVENT8, but the
northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map
accordingly.
Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5556
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
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Hudson ASL files assume the USB power event notifications are mapped
to GPE 0xb. Since that GPE is not used on this board, map these events
to GPE11. This GPE is already handled in ACPI via Method(_L0B). We
adjust this method to also notify the XHCI controller at PCI 10:0.
Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
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The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and
always had the wake source declared as GPE3. This is not the correct
wake source for all boards. On some laptops declaring a wake source is
not needed, as the wake mechanism is handled by the EC.
Move the declaration of the power button to mainboard ASL files, and
scope it as \_SB.PWRB . This also makes the naming consistent with the
examples in the ACPI spec. The wake source for the PWRB of HP Pavilion
M6 1035dx is removed, as it is incorrect.
Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5546
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
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