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path: root/src/mainboard/intel/adlrvp/memory.c
AgeCommit message (Expand)Author
2021-05-12mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVPMaulik V Vaghela
2021-03-28mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configurationMaulik V Vaghela
2021-03-28mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configurationMaulik V Vaghela
2021-03-26soc/intel/alderlake: Add provision to override Rcomp settingsSubrata Banik
2021-03-26soc/intel/alderlake: Align RcompResistor definition as per MRCSubrata Banik
2021-02-22mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17Subrata Banik
2021-02-11src: Remove unused <arch/cpu.h>Elyes HAOUAS
2021-01-25soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driverFurquan Shaikh
2020-12-01mb/intel/adlrvp: Add support for LPDDR5Sridhar Siricilla
2020-12-01mb/intel/adlrvp: Refactor lpddr4_mem_config structureSubrata Banik
2020-11-29mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVPSubrata Banik
2020-11-09mb/intel/adlrvp: Replace if-else-if ladder with switch constructSridhar Siricilla
2020-11-08mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'Subrata Banik