coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-11-23	mb: Set coreboot as DSDT's manufacturer model ID	Elyes HAOUAS
2018-11-21	ACPI: Fix DSDT's revision field	Elyes HAOUAS
2018-10-17	mb//: Clean up FADT checksum assignment	Jonathan Neuschäfer
2018-08-13	fsp_broadwell_de: Increase CONFIG_MAX_CPUS to 32	Samuel Jimenez
2018-08-13	src/mb: Remove some unneeded includes	Elyes HAOUAS
2018-05-31	cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE	Nico Huber
2018-05-08	mb/intel: Get rid of device_t	Elyes HAOUAS
2018-01-26	mb///cmos.layout: Fix the values for the console level	Arthur Heymans
2017-09-23	mb//: Remove rtc nvram configurable baud rate	Arthur Heymans
2017-07-06	mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2017-03-21	mainboards: Don’t select `CONSOLE_POST`	Paul Menzel
2017-02-20	mainboard/{google,intel}: Change config option selection	Furquan Shaikh
2016-09-15	camelbackmountain_fsp: Select SERIRQ_CONTINUOUS_MODE	Werner Zeh
2016-08-17	mainboard: Clean up boot_option/reboot_bits in cmos.layout	Nico Huber
2016-08-01	Add newlines at the end of all coreboot files	Martin Roth
2016-04-15	mainboard/intel: Add Broadwell-DE based Camelback Mountain CRB	York Yang