coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2019-11-12	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans
2019-07-20	mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`	Nico Huber
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
2019-06-05	mb/*/devicetree.cb: Remove unavailable PCIe ports	Arthur Heymans
2019-01-08	mb/{ga-g41m-es2l,d945gclf,rk886ex}: Fix devicetree	Arthur Heymans
2018-11-12	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans
2018-06-04	mb/intel: Get rid of whitespace before tab	Elyes HAOUAS
2016-12-11	nb/intel/i945: Make pci_mmio_size a devicetree parameter	Arthur Heymans
2016-09-07	mb/intel/d945gclf: Disable combined mode to fix SATA	Arthur Heymans
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-11-04	i82801gx: Handle whole FADT in southbridge.	Vladimir Serbinenko
2013-02-14	sconfig: rename lapic_cluster -> cpu_cluster	Stefan Reinauer
2013-02-14	sconfig: rename pci_domain -> domain	Stefan Reinauer
2011-03-01	Use subsystem id from devicetree.cb instead of Kconfig and move	Sven Schnelle
2010-05-05	Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster"	Patrick Georgi
2010-04-27	Since some people disapprove of white space cleanups mixed in regular commits	Stefan Reinauer
2009-11-06	Remove drivers/pci/onboard. The only purpose was for option ROMs, which are	Myles Watson
2009-11-06	Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.	Uwe Hermann
2009-10-28	Add some missing license headers, consistency fixes for others (trivial).	Uwe Hermann
2009-10-28	preliminary Intel D945GCLF Atom+i945 support.	Stefan Reinauer