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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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path:
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src
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mainboard
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intel
/
emeraldlake2
/
romstage.c
Age
Commit message (
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Author
2014-01-22
CBMEM: Replace cbmem_initialize() with cbmem_recovery()
Kyösti Mälkki
2014-01-15
Intel (sandy/ivy): Avoid calling cbmem_initialize() twice
Kyösti Mälkki
2013-11-10
sio1007: Properly build '.c' files
Marc Jones
2013-11-10
emeraldlake2: Clean up COM port enable
Marc Jones
2013-09-21
CBMEM: Always select CAR_MIGRATION
Kyösti Mälkki
2013-09-21
timestamps: Stash early timestamps in CAR_GLOBAL
Kyösti Mälkki
2013-09-21
timestamps intel: Move timestamp scratchpad to chipset
Kyösti Mälkki
2013-03-22
x86: Unify arch/io.h and arch/romcc_io.h
Stefan Reinauer
2013-02-28
CBMEM: always initialize early if the board supports it
Stefan Reinauer
2012-10-08
hpet: common ACPI generation
Patrick Georgi
2012-07-24
Drop (empty) sandybridge_late_initialization()
Stefan Reinauer
2012-07-24
Remove CMOS Extended range enable from romstage
Duncan Laurie
2012-05-03
Don't pre-enable SATA AHCI in romstage.c
Stefan Reinauer
2012-05-01
Clean up Emerald Lake 2 mainboard directory
Gabe Black
2012-05-01
Fix Sandybridge/Ivybridge mainboards according to code review
Stefan Reinauer
2012-04-30
Add support for Intel Emerald Lake 2 CRB
Stefan Reinauer