coreboot - Some coreboot project code with my work

Age	Commit message (Collapse)	Author
2019-11-04	soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig	Michael Niewöhner
	The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-29	mb/intel/icelake_rvp/../icl_y: Enable SaGv	Subrata Banik
	This patch enables SaGv on Intel ICL-Y RVP board. TEST=Able to build and boot to Chrome OS. Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-23	mb/intel/icelake_rvp: Enable dptf functionality	Sumeet Pawnikar
	Enable dptf functionality for IceLake based U and Y systems. Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/29686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-10	mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters	Aamir Bohra
	This implementation configures below parameters: 1. Enable SaGv, isclk. 2. Set Pcie rootport enable, Clock source usage and clkreq. 3. Configure SATA and LPSS controllers parameters. 4. Enable CNVI controller, configure Wifi end device under PCIE RP1. 5. Add TPM device support under GSPI1. Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-27	mb/intel/icelake_rvp: Add USB port capablity information	Aamir Bohra
	This implementation adds USB port capablity map for ICL-U and ICL-Y RVP. Change-Id: I20bb43c47439df0a25ff148eae2b3e0546e4bc63 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-23	mb/intel/icelake_rvp: Add support for ALPS touchpad	Aamir Bohra
	BUG:none TEST:Verify cursor response and button clicks Change-Id: I4085b70560e2840c71b989348f56ca907e7cea4b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29777 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-23	mb/intel/icelake_rvp: Configure eSPI IO decode range for EC	Aamir Bohra
	This implementation adds eSPI IO decode range for EC. 1. 0x800-0x8FF / 0x200-020F: EC host command range. 2. 0x900-0x9ff: EC memory map range. Change-Id: I69e6b3a83c072036c5b3ae801f8d80dfda82478e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-11-09	mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵	Subrata Banik
	generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/icelake Change-Id: I21d3818ac9e384b0dbaa330d231022bdb8b8a547 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-10-26	mainboard/intel/icelake_rvp: Do initial mainboard commit	Aamir Bohra
	Clone entirely from mainboard/intel/cannonlake_rvp commit id: af89f49b83260a04dece84b34e97560fb85d29ae List of changes on top off initial cannonlake_rvp clone 1. Rename "Cannonlake" with "Icelake". 2. Replace "cannonlake_rvp" with "icelake_rvp". 3. Rename "cnl" with "icl". 4. Remove unwanted SPD file, will add correct SPD with mainboard patches. 5. Remove NHLT related implementation. 6. Remove FSP configs, will add once FSP headers are available. 7. Removed smihandler.c, will add later if needed. Change-Id: I875972d1fb2f630bf5eb29bd955c484e7f9aa415 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/29164 Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>