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Change-Id: Id49032c0f9b701fe12873c80e1bc0e4b64ba7106
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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This CL selects the PcieRpClkReqDetect for the required root ports
which is needed to allow proper clksrc gpio configuration.
Also, sets the unused PcieClkSrcUsage to 0xFF.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe
Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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We need to configure GSPI related gpios for external EC and TPM.
Along with GSPI configuring gpios for LAN (power down), FSP_INT
and PCH_INT.
BUG=None
BRANCH=None
TEST=External EC card works and LAN is powered down.
Change-Id: I1f2d32537b56802d0631a94590a6ebe156c5cdd0
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40362
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable Wifi and Bluetooth for Jasper Lake RVP with following changes:
1. Enable related pci root ports for WLAN and BT
2. Disable unused root ports and clkreq for unused clocks
3. Configure GPIOs properly for M.2 port
BUG=None
BRANCH=None
TEST=Code compiles and able to detect Wifi/BT module on board.
Change-Id: Ifbd07022c05769c04ecd49c81a4430947125b32a
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39933
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure write protect and card detect SD Card GPIO for JSLRVP
as per schematics.
BUG=None
BRANCH=None
TEST=Build, boot JSLRVP and verified SD Card detection.
Change-Id: I8114d6980a2a542538b05f812ca2cffc15c88c22
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39492
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove extra USB port entry because it came in from copy
patch from the previous board and configure USB over-current
pins as per JSLRVP.
Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable S0ix from devicetree for JSLRVP
TEST= Build, boot JSLRVP and Verified S0ix is
working by running "echo freeze > /sys/power/state"
from kernel console.
Change-Id: Iedbd7ce9db546f8dc6cb3343fa624abde0ef0d3f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Enable audio for Jasper Lake RVP board. It has 2 Audio codec chips
connected on I2C0: DA7219 and MAX98373
1. Enable Kconfig to enable I2C drivers for both chips.
2. Make necessary devicetree changes to enable FSP UPDs and ACPI entry
for I2C0.
3. Enable audio related GPIO configurations.
BUG=None
BRANCH=None
TEST=Checked that dmic and speaker are functional on Jasper Lake RVP
Change-Id: Ibf76eb36c478bd33cbc0c86099236452b397fcc5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39695
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop
referring from soc/intel/tigerlake.
Addtionally mainboard changes are done to support build.
BUG=b:150217037
TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: Iad0b394dea017223a5b92fff0cb4c2ed1d5a7bd7
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39402
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch disables the SATA config from devicetree for JSL RVP, since we
are not planning to use the SATA storage in chrome config.
Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Configure UPDs to support Audio enablement.
Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:147436144
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Jasper Lake SOC has 8 PCIe root ports. Cleaning up the root ports
as per Jasper Lake. This patch updates the devicetree to enable WLAN
and NVME for jasperlake_rvp and removes the other root port configurations
which are not required.
Change-Id: I6c801d81ccece6b45a7c45212533bb33a6805367
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38679
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update chip files to include :
- Update chip.c based on TGL FSP
- Update chip.h based on TGL FSP
- Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update
- Update pmc_utils.c and JSL devicetree for build failure
Reference
PCH EDS#576591 vol1 rev1.2
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tigerlake SoC doesn't have GPIO defined for GPP_G. so compilation is
failing due to this.
We will update correct gpio for sd card detect once we have Jasper Lake
soc gpio patch.
partner bug for tracking: https://ticket.coreboot.org/issues/251
BUG=None
BRANCH=NONE
TEST='jslrvp' mainboard builds successfully
Change-Id: I097b2f3a4fef1a487495a4aa9d2bcf88aa64f017
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.
This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761
Below are the changes done over the copy patch:
1. Rename "Icelake" with "Jasperlake".
2. Replace "icelake_rvp" with "jasperlake_rvp".
3. Rename "icl" with "jsl".
4. Remove unwanted SPD file, add empty SPD as
placeholder.
5. Replace "soc/intel/icelake" with "soc/intel/tigerlake"
as tigerlake SOC hosts jasperlake code as well.
6. Empty romstage_fsp_params.c, to fill it later with
SOC specific config.
7. Empty GPIO configuration, to be filled as per board.
8. Change copyright year to 2019.
9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP
and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
10. Replace icl_u and icl_y variant with jslrvp variant.
11. Remove basebord gpio.c and rely on variant override.
12. Remove HDA verb table and config support.
Changes to follow on top of this:
1. Add correct memory parameters, add SPDs.
2. Clean up devicetree as per jasperlake SOC.
3. Add GPIO support.
4. Update chromeos.fmd to make 10MB BIOS region.
TEST=Build jasperlake rvp board
Change-Id: I3314215807959b7348b71933fbba98e6487c0632
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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