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Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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A recently announced Turbot system populates two Ethernet
controllers. Enable the remaining disabled PCIe port.
Also add a clarifying comment regarding the port associated
with Function 0. Coreboot must not be allowed to disable the
function which breaks PCI compatibility.
Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16429
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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- Align register values.
- Enable both EHCI and XHCI so the choice of port used can be made
at runtime. When both are enabled in devicetree, XHCI currently gets
disabled by the FSP chipset code. This can be overridden in mainboard
code or by a Kconfig entry, but there's a question about whether or not
that's desired.
- Enable function 1c.0 so the rest of the functions will be
seen, even though the function is not actually used. This is a
short-term fix, as the correct solution is to determine whether or not
any of the other functions are enabled, and not to hide function 0 if
they are. I am working on that, but I want to get this in for now.
Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7663
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Set the UPD entry based on the Kconfig value instead of having two
separate places that the value needs to be set.
Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7490
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
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No need to mark Makefiles, C files or devicetrees
executable.
Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7618
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Baytrail Gold3 FSP support memory down configuration. Update Minnow Max
to use Gold3 FSP. Set memory down data in devicetree.cb, instead of use
different FSP image.
Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/7581
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
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The entries in chip.h are used to set the UPD values. These had
originally been shortened and did not match the names of the structure
entries in vendorcode/intel/fsp/baytrail/include/fspvpd.h
This patch aligns the names.
- Update names in chip.h.
- Update names in devictree registers for bayley bay and minnow max.
- Update names in chipset_fsp_util.c
Change-Id: I8d7e34195cec2e63802d7e07e5aed71735556936
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7486
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Minnowboard Max was broken by
commit 454625c5 - intel/fsp_baytrail: Fix SMM/SMI
because TSEG wasn't set to 8MB by the FSP.
The default in the FSP is 1MB.
Change-Id: I2e671a6ca0240e931399920c62439c36133789aa
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7240
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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MinnowMax board using Intel's Bay Trail FSP
Working:
- Booting from SATA / USB / (USB3 with latest SeaBIOS)
Not working:
- Boot from SD
- S3 Suspend / Resume
***** To configure the FSP *****
Download the Bay Trail FSP and the binary config tool:
Modify the standard Bay Trail FSP:
run the bct tool with the command line options:
bct --bin <Bay Trail FSP Binary> \
--absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \
--bout <path to save the updated FSP to>
Here are the required changes for modifying the FSP manually:
Enable Memory Down: Enabled
DRAM Speed: 1066 MHz
DIMM_DWidth: x16
DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max)
tCL: 7
tRP_tRCD: 7
tWR: 8
tRRD: 6
tRTP: 4
tFAW: 27
Other FSP values can remain the same.
***** To configure the vbios *****
The vbios is in the Bay Trail FSP package.
Download Intel's "Binary Modification Program" (BMP)
Use it to disable all ports except HDMI on port B.
Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6429
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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