coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2016-03-13	northbridge/intel/i3100: Unify UDELAY selection	Stefan Reinauer
2014-12-30	intel CAR: Fix DCACHE_RAM_BASE for old sockets	Kyösti Mälkki
2014-05-03	Move ARCH_* from board/Kconfig to cpu or soc Kconfig.	Furquan Shaikh
2011-12-02	i3100: Add HAVE_HARD_RESET	Sven Schnelle
2011-03-01	Use subsystem id from devicetree.cb instead of Kconfig and move	Sven Schnelle
2010-12-08	Move "select CACHE_AS_RAM" lines from boards into CPU socket.	Uwe Hermann
2010-08-30	We call this cache as ram everywhere, so let's call it the same in Kconfig	Stefan Reinauer
2010-08-30	Fix intel mtarvon compilation by switching it over to CAR.	Stefan Reinauer
2010-08-30	Restructured all vendors' Kconfig files to no longer source the boards'	Jens Rottmann
2010-07-06	Re-integrate "USE_OPTION_TABLE" code.	Edwin Beasant
2010-03-29	This patch drops the coreboot CMOS checksum ranges from Kconfig because	Stefan Reinauer
2010-02-27	- make HAVE_HARD_RESET match what newconfig did	Patrick Georgi
2010-02-09	Move all the copies of the romstage.inc rule to	Patrick Georgi
2010-01-25	Align several kconfig options to match newconfig:	Patrick Georgi
2009-11-27	Make newconfig and kconfig agree on MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID	Patrick Georgi
2009-10-20	Fix all board names in Kconfig as per wiki / vendor website.	Uwe Hermann
2009-10-16	Set default ROM sizes per-board to match the ROM chip that came	Uwe Hermann
2009-10-15	Add CONFIG_GENERATE_* for tables so that the user can select which tables not	Myles Watson
2009-10-03	Remove duplicate and not too useful Kconfig board comments as	Uwe Hermann
2009-09-29	Fix a number of board names in Kconfig (trivial).	Uwe Hermann
2009-09-25	some progress on kconfig:	Patrick Georgi