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path: root/src/mainboard/intel/stargo2
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2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-15mainboards: align on using ACPI_Sx definitionsAaron Durbin
The mainboard_smi_sleep() function takes ACPI sleep values of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure that whatever hardware PM1 control register values are used the interface to the mainboard is the same. Move all the SMI handlers in the mainboard directory to not open code the literal values 3 and 5 for ACPI_S3 and ACPI_S5. There were a few notable exceptions where the code was attempting to use the hardware values and not the common translated values. The few users of SLEEP_STATE_X were updated to align with ACPI_SX as those defines are already equal. The removal of SLEEP_STATE_X defines is forthcoming in a subsequent patch. BUG=chrome-os-partner:54977 Change-Id: I76592c9107778cce5995e5af764760453f54dc50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15664 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-04-13mainboard/intel: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I260c1ae8d0f7306dd0c72c9ca05f0789cd915a61 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14322 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10mainboard/intel: Add Stargo2Marc Jones
The Intel Stargo2 is a communications device reference design. This mainboard uses the Sandy/Ivy Bridge and is paired with the i89xx southbridge. The FSP package is available from Intel: https://intel.com/fsp. Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/12170 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>