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BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3,
then copied ISH firmware to host file system /lib/firmware/intel/tglrvp_ish.bin
check "dmesg |grep ish", it shows:
ish-loader: ISH firmware intel/tglrvp_ish.bin loaded
cros_ec_ishtp: Chrome EC device registered
Those means shim loader in coreboot has loaded ISH firmware, and
firmware is running successfully.
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Change-Id: I1ee8050aef6ec0828f16ef2695b5347278caa820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39481
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable CNVi in devicetree and add gpio pad configs for CNVi
BUG=none
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I71146960e0d53dae87946a0365dac6f224a72391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update GPIO reset type from PLTRST to DEEP.
DEEP setting is more conservative for S3/S4/S5.
Detail information is bug.
BUG=b:151305120
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39476
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
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During intial UP4 patch, below UP3 patches merged which should be
applied for UP4.
https://review.coreboot.org/c/coreboot/+/39201
https://review.coreboot.org/c/coreboot/+/39229
Merge these patches to UP4
BUG=none
BRANCH=none
TEST=Build TGL UP4
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
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This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check for SSDT entries
for CNVi
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add LPDDR4 memory configuration for Tiger Lake UP4 platform which
includes
1. DQ/DQs Mapping
2. Board id Support
3. SPD indexing
BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial TGL UP4 RVP build enviorment
BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39363
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add additional pin mux for I2C3, I2C5 for Camera.
These pin muxes were done in FSPs, these pin muxes are for bypassing
pin muxes in FSPs.
BUG=none
BRANCH=none
TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera
Simple test method to check camera: capture image by below commands from
OS console
>media-ctl -V "\"Intel IPU6 CSI-2 5\":0 [fmt:SGRBG10/3280x2464]"
>media-ctl -V "\"Intel IPU6 CSI-2 5\":1 [fmt:SGRBG10/3280x2464]"
>media-ctl -l "\"ov8856 18-0010\":0 -> \"Intel IPU6 CSI-2 5\":0[1]"
>media-ctl -V "\"Intel IPU6 CSI2 BE\":0 [fmt:SGRBG10/3280x2464]"
>media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [crop:(0,0)/3280x2464]"
>media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [fmt:SGRBG10/3280x2464]"
>media-ctl -l "\"Intel IPU6 CSI-2 5\":1 -> \"Intel IPU6 CSI2 BE\":0[1]"
>media-ctl -l "\"Intel IPU6 CSI2 BE\":1 -> \"Intel IPU6 CSI2 BE capture\":0[1]"
>yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10
$(media-ctl -e "Intel IPU6 CSI2 BE capture")
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39201
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes
were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check FSP log or DP port
pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39229
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for Max98373 speaker amp & ALC5682 headset codec
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I013dbc6246b07a501f9bff80c2bca3594e6cc146
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Update memory parameters based on memory type supported by Tiger lake RVP
1. Update dq/dqs mappings
2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory
3. Add SPD data bin files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST= build tglrvp flash and boot to kernel
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable,
PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD
value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c.
Pin mux for ISH for TGLRVP
ISHUART0: GPP_D13, GPP_D14 as NF1
ISHI2C0: GPP_B5, GPP_B6 as NF1
ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1
BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux.
Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting.
They should be NF1.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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pin mux for IMGCLKOUT_0 and IMGCLKOUT_1
BUG=none
BRANCH=none
TEST=Build and boot to OS and check pinctl driver to check pin mux for
Image clocks pins(GPP_D4, GPP_H20)
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ifb0c2b17dd481ef6c19bdf9ee84f47ef08d7b9a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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TGLRVP uses DdiPort1Hpd and DdiPort1Ddc. So only enable them.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux
from pinctl driver.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ief6376ba59c77340e272923958b6b5f0a1456d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38529
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add MIPI camera ACPI
Update GPIO pin mux for camera
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check camera
Simple test method to check camera: capture image by below commands from
OS console
>media-ctl -V "\"Intel IPU6 CSI-2 5\":0 [fmt:SGRBG10/3280x2464]"
>media-ctl -V "\"Intel IPU6 CSI-2 5\":1 [fmt:SGRBG10/3280x2464]"
>media-ctl -l "\"ov8856 18-0010\":0 -> \"Intel IPU6 CSI-2 5\":0[1]"
>media-ctl -V "\"Intel IPU6 CSI2 BE\":0 [fmt:SGRBG10/3280x2464]"
>media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [crop:(0,0)/3280x2464]"
>media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [fmt:SGRBG10/3280x2464]"
>media-ctl -l "\"Intel IPU6 CSI-2 5\":1 -> \"Intel IPU6 CSI2 BE\":0[1]"
>media-ctl -l "\"Intel IPU6 CSI2 BE\":1 -> \"Intel IPU6 CSI2 BE capture\":0[1]"
>yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10
$(media-ctl -e "Intel IPU6 CSI2 BE capture")
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4189e96f68f0e64e0860405e00eeab84564b86be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37863
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage
device and NVMe Optane memory. Storage device uses rp9 and optane memory
uses rp11. This patch enables rp11. Please note that these two share clk pins.
This is also dependent on pciecontroller3 config to be set as 2x2 instead of
1x4 in fit configuration in IFWI.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices
from lspci
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups in coreboot so that they are mapped properly.
GPIO comuinities in coreboot should match with the kernel gpio
communities also. Kernel reads the ASL file from coreboot. This
patch adds the proper community mapping in ASL code to match with
kernel code. In gpio_soc_defs.c file we are indexing the groups
correctly. In gpio.h file we define all the gpio devices as kernel
populates sysfs with separate gpio device for each community. This
patch is created based on Intel Tiger Lake Processor PCH Datasheet
with Document number:575857 and Chapter number:27.
BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. In /sys/kernel/debug/pinctrl
verify INTC34C5:0<1-3> listing all the pins for each community.
e.g., #cat /sys/kernel/debug/pinctrl/INT34C5:00/pins should list
all the community 0 pins.
Change-Id: I40c386db060d84c1b7fba9c587f960d6a92f84ba
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Enable both SATA ports for TGLRVP.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Tigerlake RVP UP3 devicetree to reflect devices used by
tglrvp_up3.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Idd0d9efe0ab4e050d2160f7662e4dc40a002672f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37929
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38286
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.
This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761
Below are the changes done over the copy patch:
1. Rename "Icelake" with "Tigerlake".
2. Replace "icelake_rvp" with "tglrvp".
3. Rename "icl" with "tgl".
4. Remove unwanted SPD file, add empty SPD as
placeholder.
5. Replace "soc/intel/icelake" with "soc/intel/tigerlake".
6. Empty romstage_fsp_params.c, to fill it later with
SOC specific config.
7. Empty GPIO configuration, to be filled as per board.
8. Change copyright year to 2019.
9. Add board support namely BOARD_INTEL_TGLRVP_UP3
10. Replace icl_u and icl_y variant with tglrvp variant.
11. Remove basebord gpio.c and rely on variant override.
12. Remove HDA verb table and config support.
Changes to follow on top of this:
1. Add correct memory parameters, add SPDs.
2. Clean up devicetree as per tigerlake SOC.
3. Add GPIO support.
4. Update chromeos.fmd to make 32MB BIOS region.
5. clean up and make empty devicetree setting
TEST=Build tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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