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2014-08-22Remove dead video.aslVladimir Serbinenko
Change-Id: Iadaa6172347ebb7d367d1faa6ed9462fff07d7e6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6730 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18azalia: Move shared variable to separate fileVladimir Serbinenko
Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6695 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-18mainboard/intel/mohonpeak: code cleanupMartin Roth
Code cleanup requested in commit 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" - Change com2 to COM2 in Kconfig text - clean up includes of headers - fix whitespace Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6607 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18southbridge/intel/fsp_rangeley: fix to include irqroute.h twiceMartin Roth
This matches what was done on baytrail in commit bfca984b - soc/intel/fsp_baytrail: set up for including irqroute.h twice irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18mainboard/XXX/YYY/dsdt.asl: Whitespace fixMartin Roth
Use tab between "COREBOOT", and comment. This fix was requested in 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" Change-Id: If9fb6158cca95341ab57db1125e85648b616b72c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6601 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-15intel/cpu: rename car.h to romstage.hAaron Durbin
This header has nothing to do with cache-as-ram. Therefore, 'car' is the wrong term to use. It is about providing a prototype for *romstage*. Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6661 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14Intel: Add common header file for CAR setupEdward O'Callaghan
When passing '-ffreestanding' the 'main' romstage.c may no longer necessarily be considered the entry point. From the C specification in 5.1.2.1 Freestanding environment; "In a freestanding environment (in which C program execution may take place without any benefit of an operating system), the name and type of the function called at program startup are implementation-defined." Clang complains about these being missing as Clang is somewhat more strict about the spec than GNU/GCC is. An advantage here is that a different entry-point type-signature shall now be warned about at compile time. Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12mainboard/intel/minnowmax: clean up includes & whitespaceMartin Roth
Clean up as requested in commit e6df041b. No functional changes. Change-Id: Iec3f7ee25fd8351c7e13d660e2df6461f7745478 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6597 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-11bayleybay_fsp: Add bakersport board variantMartin Roth
The Bakersport board is a variant of the Bayley Bay mainboard that uses one ECC DIMM instead of two non-ECC dimms. This commit uses the Bayley Bay mainboard directory and modifies the required pieces to add the Bakersport board variant. It disables the second DIMM, points to an ECC version of the FSP, and sets the board name to be Bakersport instead of Bayley Bay. All of the code is still contained in the bayleybay_fsp directory. It seems like duplicating the whole directory for the one line of code that's actually different between the two platforms. Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5983 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-08-11mainboard/intel/minnowmax: Add MinnowMax mainboardMartin Roth
MinnowMax board using Intel's Bay Trail FSP Working: - Booting from SATA / USB / (USB3 with latest SeaBIOS) Not working: - Boot from SD - S3 Suspend / Resume ***** To configure the FSP ***** Download the Bay Trail FSP and the binary config tool: Modify the standard Bay Trail FSP: run the bct tool with the command line options: bct --bin <Bay Trail FSP Binary> \ --absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \ --bout <path to save the updated FSP to> Here are the required changes for modifying the FSP manually: Enable Memory Down: Enabled DRAM Speed: 1066 MHz DIMM_DWidth: x16 DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max) tCL: 7 tRP_tRCD: 7 tWR: 8 tRRD: 6 tRTP: 4 tFAW: 27 Other FSP values can remain the same. ***** To configure the vbios ***** The vbios is in the Bay Trail FSP package. Download Intel's "Binary Modification Program" (BMP) Use it to disable all ports except HDMI on port B. Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6429 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-11soc/intel/fsp_baytrail: set up for including irqroute.h twiceMartin Roth
irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Add a time. Change-Id: I882cbbff0f73bdb170bd0f1053767893722dc60a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6572 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-09intel/eagleheights/Kconfig: Do not set twice MMCONF_BASE_ADDRESSDaniele Forsi
Remove the lines added in an apparently unrelated commit 53ad9f58 (Make CONFIG_HAVE_HIGH_TABLES consistent in where and how it is set.) which touched the symbol HAVE_HIGH_TABLES in all files except this one and keep those added the same day in commit 6842c029 (Remove MAINBOARD_OPTIONS, which is a relic from early kconfig development.) Change-Id: Ib055c25a0a0795a50a36e65218c8f31e921f1502 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6417 Tested-by: build bot (Jenkins) Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-03sandy/ivybridge: Make UMA size configurable.Vladimir Serbinenko
Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6470 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-30mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000Martin Roth
Add the Mohon Peak CRB. Updates to come. Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6371 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-18mainboard: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: If29a70be4fb56ebb0dbf6d510412cbe2f34480ef Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6291 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-18src/superio/smsc/lpc47m15x: Avoid #include early_serial.cEdward O'Callaghan
Provide proper header and function type-signatures for Super I/O romstage component. Fix mainboard's bogous romstage component to match. Change-Id: Icd02199690d0c428b2daadf702d50714dc367692 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5924 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-17mainboard,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ib531a54db7df6b49a6218f689dcaab712e9dfb01 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6292 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-08mainboard: Trivial - drop trailing blank lines at EOF in .hEdward O'Callaghan
Change-Id: I4a4ee99468e5f1dae8412ae565a34290493db726 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6201 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-07-08mainboard: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I05d6d22664155ac8478e665733f816776e277c22 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6200 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05Intel Lynx Point boards: Kconfig: Add `HAVE_ME_BIN`Paul Menzel
Change-Id: Ib7d2a5c14675427fe9556a6b81ed5397f17937d8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6049 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05Intel Lynx Point boards: Kconfig: Add `HAVE_IFD_BIN`Paul Menzel
Change-Id: I0ea09d75cb05687407fb152642578e19824d1c4c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6048 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05intel: Make monotonic timer a first class citizenEdward O'Callaghan
The monotonic time now needs to be a first class citizen in Coreboot as it is a hard dependency of the drivers/spi flash command polling function. Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6135 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-26bayleybay_fsp: Switch from EHCI controller to XHCIMartin Roth
- Disable the EHCI controller and enable the XHCI controller. SeaBIOS has been tested on the board and boots an OS from a flashdrive at SuperSpeed. This also enables the top USB port on the 2-port stack, which goes through a High Speed Inter-Chip port. The HSIC port is only enabled through the XHCI device. Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6106 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2014-06-25i945 boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki
Change-Id: I1bbcba086f841a90544b827ae807a3c351d19d21 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25sandy/ivy boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki
Like with other more recent boards already using DYNAMIC_CBMEM, the pointer to TOC is no longer stored in GNVS for ACPI. Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6034 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25i945 boards: Drop disabled ram_check() callsKyösti Mälkki
This code would not get enabled just by flipping the options in menuconfig, also ramcheck() no longer test the range like the parameters would imply. We should add non-destructive ram_check() on S3 resume path to verify memory controller configuration has been properly recovered. Change-Id: Ie4675c4770146c4312cdfbc81afa19f243f90ee4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6027 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-23bayleybay_fsp: Add comments for the MMC/SD devices in devicetreeMartin Roth
This just adds some additional comments for the EMMC / SD / SDIO PCI devices in devicetree. The documentation states that the EMMC 4.1 device shouldn't be used, but it's available to enable in the FSP. Because it can be enabled, I've included it in the devicetree even though its use is discouraged. Change-Id: I64633fe1908368f69a8d4031aa900b0bceb2189e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6089 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21Remove guarding #includes by CONFIG_FOO combinationsEdward O'Callaghan
First of many to remove guarding the inclusion of headers based on CONFIG_ options. This *potentially* could hide issues such as functions being swapped from under our feet, since different runtime behaviour could be declared with the function same name and type-signature. Hence, depending on the header we happen to get may change runtime behaviour. Change-Id: Ife56801c783c44e1882abef711e09b85b7f295a4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6055 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21intel boards: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6071 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20sandy/ivy boards: Use acpi_s3_resume_allowed()Kyösti Mälkki
Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6063 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20intel/i945 gm45: Use acpi_s3_resume_allowed()Kyösti Mälkki
Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6061 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-18intel/bayleybay_fsp: Drop redundant EARLY_CBMEM_INITKyösti Mälkki
This is implied from DYNAMIC_CBMEM from soc/. Change-Id: I8cd8c2dff723950377998750377a3168f1f5fc5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6029 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-18mainboard: Clear up remaining SIO_PORT from KconfigEdward O'Callaghan
Push back any board specific values back into romstage.c #defines and drop any remaining fragments of CONFIG_SIO_PORT in-tree. Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6045 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6032 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-13fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOTMartin Roth
While pushing the fsp_baytrail code, it was requested that we change CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT. These were missed in the change. Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5972 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-12bayleybay_fsp Kconfig: Remove unnecessary overridesMartin Roth
Use the default mmconf base address and fsp locations. Change-Id: Ia9116b0f0fc799592df2a10b10e086cfc88b394c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5982 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03superio/smsc/smscsuperio: Make romstage linkable with headerEdward O'Callaghan
Rewrite smsc/smscsuperio romstage component to be more consistent and provide header there-by removing #include's of early_serial.c's in mainboard's. Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5915 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-30intel/bayleybay: Add Intel's Bayley Bay mainboardMartin Roth
Bay Trail-I Platform – Bayley Bay-I Customer Reference Board The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform. It is designed to support the Bay Trail-I SoC. This implementation uses the Intel FSP (Vist the Intel FSP website for details on FSP architecture and support). This code does not currently support S3. All other features and IO ports are functional. Booted on Ubuntu 14.04, Mint 16, Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and other tests pass. Notes: - Generates a 2MB binary to be flashed to the upper 2MB of the ROM, to preserve the existing Intel Flash Descriptor & TXE binary. - Tested with B0 & B3 Baytrail I parts Board support page will be updated on acceptance. Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23mainboard/intel/emeraldlake2 Fix usage of GNU field designator extEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Idda1a49277c156670014fac27b9f1c378f8df0cd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5827 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23mainboard/intel/baskingridge Fix usage of GNU field designator extEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I61fe91e467c29f144323af9c4612420f322098b4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5826 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23mainboard/intel/wtm2: Fix usage of GNU field designator extensionEdward O'Callaghan
Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I46fad8d236c620ee5dbeb24f4517f20f00db839f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-20drivers: Drop GbE stub driversEdward O'Callaghan
These NIC stub drivers were to initialize the Gigabit Ethernet adapters just enough to keep coreboot from trying to execute an option ROM. However this is no longer required as non-VGA option roms are not ran; See: b32816e Remove PCI_ROM_RUN option Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5777 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-19intel: Remove GFXUMA and related global variablesKyösti Mälkki
Remove use of global variables uma_memory_base and uma_memory_size from builds with Intel northbridges, as these variables can be kept within the chipset or even as stack locals. Intel platforms have no functional implemenation for option GFXUMA. If we did implement some choice between external and integrated graphics, it needs to be named in less obscure fashion. Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5720 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth
CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09Squelch some warnings from KconfigKyösti Mälkki
Overriding global config entries in mainboard directory Kconfig files often raise unnecessary warnings. Squelch some of those. Change-Id: Ib5127672ae068670028aa25c8ccb5366277622f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5699 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08ChromeOS boards: Always build code for bootmode strapsKyösti Mälkki
Leave it under BOOTMODE_STRAPS to control whether these have any functional meaning on the build. Change-Id: Ieb59aa7ab4b1e8da6a1002e7a8e5462eb7988d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08ChromeOS boards: Fix includesKyösti Mälkki
Change-Id: Ib8448f3d36a23538cd9fea897f09da3ec4ad007a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08Declare get_write_protect_state() without ChromeOSKyösti Mälkki
Change-Id: I72471ac68088cd26f8277b27b75b7d44ad72cfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08ChromeOS boards: Use explicit include of chromeos.cKyösti Mälkki
Change-Id: I7b3d044fad1d6973910e9bef347478a45c149a4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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