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There's no need to write the GDCRTRAININGRESULT registers after raminit.
Change-Id: If604920fe7a3bee96f72f8aff5e96f0e25548f18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50534
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch allows overriding GPIO PM miscconfig register for each
GPIO community to avoid dynamic clock gating.
TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0]
are set to '0'.
Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch disables the unsued CPU PCIe RP for shadowmountain.
TEST= Boot shadowmountain and verify the device is disabled.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ide2badb06178fca8ff5cf51d8573a14635e190cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51772
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, we used to stitch extra VBT files to ADLRVP build using
Makefile. With enablement of emerge build, we should be able to
integrate more than 1 VBT binaries using ebuild.
This removing these lines to avoid compilation issues in emerge builds
BUG=None
BRANCH=None
TEST=Check if compilation passes on emerge build. Stitched additional
VBT files using emerge and checked that coreboot picks up correct VBT.
Change-Id: I69f1cc6c07415515ff85180fdd7cc5de11b4d805
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Add function to allow overriding the RcompResistor and
RcompTarget UPDs from mainboard if required.
Mainboard users can pass required rcomp from memory.c file.
Refactor ddr_config structure to take out rcomp related variable
outside for all memory type to override if required.
BUG=b:182772421
TEST=Able to override the default RcompResistor and RcompTarget
values.
Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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List of changes:
1. Alder Lake MRC is expecting a RcompResistor value of word width.
Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot
is passing an array of RcompResistor which is not completely in use.
Note: Rcomp resistor value represents rcomp resistor attached to
the DDR_COMP pins on the SoC.
2. Also, remove usage of '&' with memcpy the required value into
RcompTarget array.
3. Also, update RcompResistor value for ADLRVP.
BUG=b:183341229
TEST=Enable FSP debug log to verify the override value for
RcompResistor is reflecting correctly.
Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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With this change, only raminit.c uses pei_data.h definitions. With MRC
cornered, making it optional is just a matter of writing a replacement.
USB config definitions will be moved to Lynx Point code in a follow-up.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.
BUG=None
TEST=Verified BT offload working on ADL RVP
Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com>
Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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It's common to use the raw, unshifted I2C address in coreboot. Adapt
mainboards accordingly and perform the shift in MRC glue code.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Do not use the same name as the non-LP GPIO config. This allows checking
at build-time that a mainboard uses the correct GPIO config format.
Without this commit, there are no build-time errors when using the wrong
format of GPIO config, but there would be undefined behavior at runtime.
Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after
toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the
USB config arrays for asrock/b85m_pro4). In both cases, building failed
because the necessary GPIO config global is not defined, as expected.
Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set chipset_lockdown in devicetree for recommended security settings.
Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to
a struct instead of an array, and update all the mainboards accordingly.
Currently, the only board with memory-down in the tree is google/slippy.
Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts
the channel population accordingly. Then, northbridge code reads the SPD
file and uses the index that was read in `mb_get_spd_map`, and copies it
to channel 0 slot 0 unconditionally. MRC only uses the first position of
the `spd_data` array, and ignores the other positions. In coreboot code,
`setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has
to account for this.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In pursuit of the goal of eliminating the proliferation of raw region
devices to represent CBFS files outside of the CBFS core code, this
patch removes the get_spd_cbfs_rdev() API and instead replaces it with
spd_cbfs_map() which will find and map the SPD file in one go and return
a pointer to the relevant section. (This makes it impossible to unmap
the mapping again, which all but one of the users didn't bother to do
anyway since the API is only used on platforms with memory-mapped
flash. Presumably this will stay that way in the future so this is not
something worth worrying about.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch sets the HDMI audio mode to 8T as required by the latest FSP
version v2081_02
TEST: HDMI audio codecs detection is failing without this change.
Change-Id: Ie5a825da7d199c9ee61e64d8f4ee7dec28fdaacd
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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This patch disables the xDCI which is causing PC8 to PC10 state
transitions during sleep.
TEST: Confirmed that the transition is happening with this change.
Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 4 and provide the reset GPIO / src clk pin.
BUG=none
TEST=Boot to OS, verify the link is in L2 state during S0ix.
Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.
Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the CNVi Bt PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.
Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add support to pick the right vbt from cbfs according to
SKU-ID.
Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the adlrvp mainboard.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Function is identical for all mainboards, so factor it out.
Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch adds the changes to enable the TCSS.
BUG=b:175808146
TEST= Boot shadowmountain board, Test the functionality of the Type-C
ports on both the mainboard and daughterboard by plugging in the Type-C
devices and verified the devices are detected via EC console and in the
OS.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced.
Just change the default value to 'y'.
Change-Id: Ie4248700f5ab5168bff551b740d347713273763c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Pineview does not support PEG.
Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is a cosmetic change.
Make the formatting consistent with the rest of the tree.
Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is to align with newer platforms.
Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit d510b60f5b4eee6c165039be4acbe89ff25d8a4a.
This patch includes the DSDT ASL code for shadowmountain board.
BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch includes the ramstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per CL:2641346, update GBB flag names:
GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW
GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW
BUG=b:179458327
TEST=make clean && make test-abuild
BRANCH=none
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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List of changes:
1. Add mainboard Kconfig to Kconfig.name files
2. Handle mainboard names in Kconfig file for adlrvp
3. Created a new devicetree.cb for Adlrvp-m.
3. Add override devicetree for ADL-M RVP.
4. Configure proper PCI and USB ports as per schematics for ADL-M
BUG=None
BRANCH=None
TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec.
Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49871
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Ensure the code gets build-tested for CONFIG_ENABLE_FSP_MEMORY_DOWN=n.
Change-Id: I6213e3e0ea3b2acfc97017739ac069ee3811d742
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch includes the romstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some (notably older Intel) boards use a tabular description of irq
routing that we want to keep pristine no matter what clang-format
considers correct (as that's ugly).
Change-Id: I259255a9f60208c659b658ecb81535e84a2aaa8c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Assign 7-bit address of the targeted slave SPD.
TEST=Able to read correct SPD data from SMBUS.
Change-Id: If24e61b583638be7c055541c6eb126da28b542f6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=Ensure SMBUS CLK/DATA GPIO is in NF1.
Change-Id: Id615462cc21fc24e7ec6ef16274d784d41bd9bd4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'
Change-Id: Id2aa085a4762355d9fb1628df40f7b43fbc81fc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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With this selected, chromeos_reserve_ram_oops() is a no-op.
Change-Id: I2f3b7b3c4a9549a14f2ba039c769546f9698409a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because
Lynxpoint uses a different value. Also drop unnecessary includes.
Tested with BUILD_TIMELESS=1, Google Tidus remains identical.
Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Intel WTM2 remains identical.
Change-Id: I422421cc3c336a7a1aceaff7b37ab7c82f64a03f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50067
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename structs, types and functions to match Lynx Point's names.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50064
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I659835354570fb1d4860fcbddf2a51831170a374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.
To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.
Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Desktop boards do not have any backlight control.
Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Platform code will overwrite these values anyway, so do not program them
in mainboards.
Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Was copy-pasted from i82801ix and no mainboard actually needs it.
Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49279
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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