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2015-04-07broadwell: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns broadwell to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Auron and Samus. Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224507 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-31cbfs: remove cbfs_core.h includesAaron Durbin
Some of the files which include cbfs_core.h don't even need the header definition while others just need the cbfs API which can be obtained from cbfs.h. Change-Id: I34f3b7c67f64380dcf957e662ffca2baefc31a90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9126 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-12intel/fsp_baytrail: Add PCI Root Port IRQ RoutingMartin Roth
This change generates the ASL tables needed for the PCIe bridge routing. It generates this ASL (swizzled for each of the 8 functions) Name(RP1P, Package() { Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, }) Name(RP1A, Package() { Package() {0x0000ffff, 0, 0, 20 }, Package() {0x0000ffff, 1, 0, 21 }, Package() {0x0000ffff, 2, 0, 22 }, Package() {0x0000ffff, 3, 0, 23 }, }) Device(RP01) { Name(_ADR, 0x1c0001) Name(_PRW, Package() { 0, 0 }) Method(_PRT,0) { If(PICM) { Return (RP1A) } Else { Return (RP1P) } } } Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-08device: drop i915 specific headers from resource allocator includesStefan Reinauer
src/include/device/ is the place for include files of the resource allocator. Hence, drop the i915 include file copies and use the ones supplied with the i915 driver instead. The only remaining user of this was the Intel Whitetip Mountain 2 reference board, all other occurences have been previously fixed already. Change-Id: Ib9f72df4e8f847597508971e9dbf671f49019767 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8140 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05mainboard: Do not redefine DRIVERS_PS2_KEYBOARD Kconfig variableAlexandru Gagniuc
Change-Id: Icc603dfe92360d978221a25ad28517da43942bea Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8498 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-24(bakersport|bayleybay)_fsp: Do not force a default loglevelAlexandru Gagniuc
DEFAULT_CONSOLE_LOGLEVEL_* is supposed to be selected by the user, and should not be overriden by any other part of the tree. As such, remove the selection of DEFAULT_CONSOLE_LOGLEVEL_7 from these two boards. Change-Id: I194a71b371b184e81a16fec2bd21f1b0deb4ebbf Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8486 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24mainboard: Do not redefine CONSOLE_POST Kconfig variableAlexandru Gagniuc
This option is already defined in console/Kconfig, and is intended to be controlled by the user. Only six boards in the entire tree redefined it, so remove the definition from those boards. Change-Id: I3a65444f63c93c01d78569a9a7eb01158fb290bd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8457 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24soc/fsp_baytrail: Fix use of microcode-related Kconfig variablesAlexandru Gagniuc
SUPPORT_CPU_UCODE_IN_CBFS is a deprecated option now that all CPUs with updateable microcode (except AGESA) load microcode from CBFS. CPU_MICROCODE_ADDED_DURING_BUILD is a state variable that is set based on user's choice in the microcode menu and should not be changed directly. Eliminate INCLUDE_MICROCODE_IN_BUILD variable, whose use directly interferes with the microcode mechanism, remove selection of CPU_MICROCODE_ADDED_DURING_BUILD, and do not depend SUPPORT_CPU_UCODE_IN_CBFS on anything. This makes usage of the microcode mechanism consistent with other CPUs in the tree. This incorrect usage of the Kconfig variables was hiding the fact that some of the microcode files present in fsp_baytrail/microcode_blob.c were not present in the tree. Change-Id: I71cb3f834c22c0363a20bd469797a9f51c215371 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8422 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-02-09Intel FSP platforms: Fix timestampsKyösti Mälkki
Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR. Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8024 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-06mainboard: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the mainboard code to use printk() on all non-ROMCC boards. Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8111 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06doxygen fixes: fix parameter names to match the functionsMartin Roth
The doxygen parameter names in the comments no longer matched the functions they were attached to. Doxygen complains about extra parameter comments and uncommented parameters in the functions. Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8101 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06mainboard/*/romstage.c: Sanitize system header inclusionsEdward O'Callaghan
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-04superio/intel/i3100: Use link-time symbol over .c includesEdward O'Callaghan
Change-Id: I83db9b189e672b0e1f25bc42b73639c375bea3e5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8054 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04mainboard: Sanitize some superio include paths to be non-localEdward O'Callaghan
This brings mainboard up to being consistent tree-wide now for all superio header path inclusions. Change-Id: I00a806ce209ba363c62e3ddd49db9bf599f32149 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8052 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04wtm2: Fix issues with USB in firmwareDuncan Laurie
XHCI driver was not enabled in libpayload and some ports were disabled that should be enabled. The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to properly indicate unused so crossystem does not attempt to export GPIO number 255 in the kernel and trigger a warning. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 Original-Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/203184 Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 328362469b00c9467908a7d18a031fee73753def) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I91ef865c44d3c73b0d74c9eaf1fbf2fb5e894434 Reviewed-on: http://review.coreboot.org/8047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-04wtm2: Convert to use soc/intel/broadwellDuncan Laurie
Convert wtm2 board to use the broadwell soc chipset. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 with haswell and broadwell CQ-DEPEND=CL:201067 CQ-DEPEND=CL:*164226 Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201070 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda Reviewed-on: http://review.coreboot.org/8001 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-30intel CAR: Fix DCACHE_RAM_BASE for old socketsKyösti Mälkki
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored and was not correctly set on affected sockets and boards. It was still referenced in romstage linker script. This was discovered by clang builds failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed. The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken from intel/cpu/cache_as_ram.inc. Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7887 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19fsp_baytrail: Remove GPIO_NC1 #defineMartin Roth
The GPIO_NC1 #define was added to handle GPIOs that are not on func0. This is already handled elsewhere in the GPIO code, so is not needed. - Remove the single GPIO_NC1 from platforms using fsp_baytrail - Revert the GPIO_INPUT_PU_10k #define to remove the _func argument. Update everywhere this macro is called. - Remove GPIO_NC1 Change-Id: I32f337af7bc88eab821d9a8c375145b45718275f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7849 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-18Drop Intel E7520 and E7525 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Also drop unused dependencies Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7836 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18intel/truxton: Un-romcc-ify boardStefan Reinauer
Change-Id: Iaf1756321960041f6a152d5dd4c9108291f51300 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7852 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-17intel/minnowmax: Determine board type from GPIOsMartin Roth
SSUS GPIO 5 reflects the Minnowboard Max SKU: --- GPIO 5 low is a 1GB board --- GPIO 5 high is a 2GB (or 4GB in the future) board. This allows us to determine the board type at runtime and configure the FSP appropriately. Change-Id: I9f75df5413d23d63280b601457ea9a1ff020d717 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7797 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-12-16CBMEM console: Fix boards with BROKEN_CAR_MIGRATEKyösti Mälkki
There is no need to call cbmemc_reinit() exclusively in romstage, that is done as part of the CAR migration of cbmem_recovery(). CBMEM console for romstage remains disabled for boards flagged with BROKEN_CAR_MIGRATE, but with this change it is possible to have it for ramstage. Change-Id: I48c4afcd847d0d5f8864d23c0786935341e3f752 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-16Intel FSP: Move to DYNAMIC_CBMEMKyösti Mälkki
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT is not enough to disable CBMEM console for romstage on these platforms. To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy. Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-09fsp platfoms: add prototype & consolidate main entry-pointMartin Roth
- In '-ffreestanding' main() is just as any other function and so it needs a type-signature. Fixes a clang warning. - Bay Trail and Rangeley have the updated romstage.c with the code moved into the chipset, put the prototype in romstage.c. - The sandybridge code has not been updated, so the prototype for it goes into chipset_fsp_util.h, next to the prototype for romstage_main_continue. - Correct the return value of baytrail main() from void * to void and remove the unnecessary asmlinkage tag. I'm surprised that this didn't generate a warning... Change-Id: I85ac0797d1e55d2b7ffdca039a52820d7827e704 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7724 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-06Remove IRQ_SLOT_COUNT on all boards without PIRQ table.Vladimir Serbinenko
This config is used only to generate PIRQ table. If no such table is supplied there is no need for config. Change-Id: I537d440f53019a6bf7f190446074e75e7420545a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7566 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-06fsp_baytrail: Allow selection of USB controller by get_optionMartin Roth
It was requested to be able to update XHCI vs EHCI via get_option, so I've added it here for minnow max. This could get moved to the chipset_fsp_util.c file later, but I'm adding it here for now. More checking needs to be added to this: - Are both controllers enabled in devicetree? If not, we don't want to allow the switch. Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7633 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-06intel/minnowmax: Update devicetreeMartin Roth
- Align register values. - Enable both EHCI and XHCI so the choice of port used can be made at runtime. When both are enabled in devicetree, XHCI currently gets disabled by the FSP chipset code. This can be overridden in mainboard code or by a Kconfig entry, but there's a question about whether or not that's desired. - Enable function 1c.0 so the rest of the functions will be seen, even though the function is not actually used. This is a short-term fix, as the correct solution is to determine whether or not any of the other functions are enabled, and not to hide function 0 if they are. I am working on that, but I want to get this in for now. Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7663 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05minnowmax board: Update KconfigMartin Roth
- The ROM chip is 8MB, not 4MB. - Default to the 2GB SKU instead of 1GB - that's what's out right now. - Set CBFS size to 3MB - that's what the firmware descriptor is set to. Change-Id: Ic77f5c1e898dca39de573623707ff5f5e5ca9682 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7649 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05fsp_baytrail: remove register option for TSEG sizeMartin Roth
Set the UPD entry based on the Kconfig value instead of having two separate places that the value needs to be set. Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7490 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2014-12-03i945: Consolidate acpi/platform.aslVladimir Serbinenko
Change-Id: Iccb2dda8a427e483c04693e46b00e0bc2452a26b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7086 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-03i82801gx: Enable upper CMOS in bootblock.Vladimir Serbinenko
Otherwise checksum may not work correctly on early stages. For compatibility with old bootblocks also enable it early in romstage. Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-01Mark non-executable files non-executablePatrick Georgi
No need to mark Makefiles, C files or devicetrees executable. Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30Replace hlt() loops with halt()Patrick Georgi
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-29mainboard/intel/minnowmax: use Baytrail Gold3 FSPYork Yang
Baytrail Gold3 FSP support memory down configuration. Update Minnow Max to use Gold3 FSP. Set memory down data in devicetree.cb, instead of use different FSP image. Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/7581 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-11-28ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. See commit a0b4a8d. Change-Id: Iae82498ab729df5682d89e66bb9de96457e91619 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7465 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-23sandy/ivy/nehalem: Remerge interrupt handlingVladimir Serbinenko
On those chipsets the pins are just a legacy concept. Real interrupts are messages on corresponding busses or some internal logic of chipset. Hence interrupt routing isn't anymore board-specific (dependent on layout) but depends only on configuration. Rather than attempting to sync real config, ACPI and legacy descriptors, just use the same interrupt routing per chipset covering all possible devices. The only part which remains board-specific are LPC and PCI interrupts. Interrupt balancing may suffer from such merge but: a) Doesn't seem to be the case of this map on current systems b) Almost all OS use MSI nowadays bypassing this stuff completely c) If we want a good balancing we need to take into account that e.g. wlan card may be placed in a different slot and so would require complicated balancing on runtime. It's difficult to maintain with almost no benefit. Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7130 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-20mainboard/intel/cougar_canyon2/romstage.c: Missing prototypeEdward O'Callaghan
Fix warning thrown by Clang due to missing prototype for main entry point function in -ffreestanding. main() is as any other function in freestanding and so a prototype is strictly needed. Change-Id: Icb29ced0306d5089049a35b1d8862f86a555ff1f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7517 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-19fsp_baytrail: Update chip.h UPD entries to match names in fspvpd.hMartin Roth
The entries in chip.h are used to set the UPD values. These had originally been shortened and did not match the names of the structure entries in vendorcode/intel/fsp/baytrail/include/fspvpd.h This patch aligns the names. - Update names in chip.h. - Update names in devictree registers for bayley bay and minnow max. - Update names in chipset_fsp_util.c Change-Id: I8d7e34195cec2e63802d7e07e5aed71735556936 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7486 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-15fsp: Change mobo partnumbers to reflect that it's running code FSP variantVladimir Serbinenko
Change-Id: I7c823550bf77b03907fa8940a8800658d66d6786 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7183 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-15mainboard/*/debug.c: Remove duplicate or dead codeEdward O'Callaghan
We already have these implemented in 'lib/debug.c'. Will fix '.c' includes in follow ups. Change-Id: I1586d8864db7f93515214ef9a4458ebc618bf61c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7316 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-11-09i945: consolidate sb & nb early initsVladimir Serbinenko
Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7062 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-09i945: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Idc3522807b17e56bdaf8f04b4bd68c6ed9777363 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7110 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-08fsp_rangeley: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7046 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-08bd82x6x: Move to common FADT.Vladimir Serbinenko
Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7200 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-04i82801gx: Handle whole FADT in southbridge.Vladimir Serbinenko
Do all the handling in SB code with few parameters from devicetree.cb instead of having mobo callbacks. Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7199 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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