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path: root/src/mainboard/intel
AgeCommit message (Expand)Author
2016-09-15kunimitsu: Add FSP 2.0 support in romstageRizwan Qureshi
2016-09-14mainboard/intel/amenia: Configure PERST_0 pinVaibhav Shankar
2016-09-14mainboards/apollolake: Set RAPL power limit PL1 value to 12W.Sumeet Pawnikar
2016-09-12kunimitsu: Add initial FSP2.0 supportRizwan Qureshi
2016-09-07mb/intel/d945gclf: Disable combined mode to fix SATAArthur Heymans
2016-09-05intel/minnowmax: Clean up whitespaceMarshall Dawson
2016-09-04intel/minnowmax: Enable all PCIe portsMarshall Dawson
2016-09-04intel/minnowmax: Program GPIO for power LEDMarshall Dawson
2016-09-02drivers/intel/fsp2_0: Make FSP Headers Consumable out of BoxBrandon Breitenstein
2016-08-31i945: Enable changing VRAM sizeArthur Heymans
2016-08-31mainboard/*/Kconfig: Set GBB_HWID where missingPatrick Georgi
2016-08-25vboot: consolidate google_chromeec_early_init() callsAaron Durbin
2016-08-18Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUSAaron Durbin
2016-08-18intel/amenia: Update eMMC DLL settingsBora Guvendik
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
2016-08-11intel/amenia: Add MAINBOARD_FAMILY for ameniaBora Guvendik
2016-08-11intel/amenia: set default value for BOOT_MEDIA_SPI_BUSBora Guvendik
2016-08-11intel/amenia: Select UART_FOR_CONSOLE for ameniaBora Guvendik
2016-08-11intel/amenia: Update flash size to 16MBBora Guvendik
2016-08-08skylake/devicetree: Add PIRQ Routing programmingBarnali Sarkar
2016-08-05soc/intel/quark: Add FSP 2.0 romstage supportLee Leahy
2016-08-05soc/intel/quark: Add FSP 2.0 boot block supportLee Leahy
2016-08-04chromeec: Chrome EC firmware source selection for EC and PD firmwaresPaul Kocialkowski
2016-08-03mainboard/intel/galileo: Add FSP 2.0 Kconfig supportLee Leahy
2016-08-03mainboard/intel/galileo: Remove use of EDK-II macros & data typesLee Leahy
2016-08-02google/lars & intel/kunimitsu: Disable EC buildMartin Roth
2016-08-02intel/amenia: Add GPIO changes to assert SLP_S0/Reset signalShankar, Vaibhav
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
2016-07-31intel/amenia: Enable DPTF in mainboardShaunak Saha
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
2016-07-31intel/wifi: Include conditionally in the buildKyösti Mälkki
2016-07-30chromeos mainboards: remove chromeos.aslAaron Durbin
2016-07-28skylake/devicetree: Add LPC EC decode rangeSubrata Banik
2016-07-28skylake/mainboard: Define mainboard hook in bootblockSubrata Banik
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
2016-07-28vboot: Separate vboot from chromeosFurquan Shaikh
2016-07-25skylake: Move CHROMEOS config to SoCFurquan Shaikh
2016-07-25apollolake: Move CHROMEOS config to SoCFurquan Shaikh
2016-07-25intel/amenia: Add chromeos.c to verstageFurquan Shaikh
2016-07-22intel/amenia: Write protect GPIO relative to bank offsetsselvar2
2016-07-19intel/amenia: Add DA7219 support in acpiHarsha Priya
2016-07-15intel/amenia: Add wake-up from lid openShaunak Saha
2016-07-15soc/intel/apollolake: Consolidate ISH enablingAndrey Petrov
2016-07-15mainboards/skylake: use common Chrome EC SMI helpersAaron Durbin
2016-07-15mainboards/apollolake: use common Chrome EC SMI helpersAaron Durbin
2016-07-15mainboards: remove direct acpi_slp_type usageAaron Durbin
2016-07-15mainboards: align on using ACPI_Sx definitionsAaron Durbin
2016-07-15Google Mainboards: Increase RO coreboot size on flashDaisuke Nojiri
2016-07-14intel/amenia: Add mainboard SMI handlerShaunak Saha
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