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2016-03-09mainboard/intel/apollolake_rvp: Add memory training configLance Zhao
Pass memory training information to MemoryInit, so memory training can be completed. Change-Id: Icb1bf308b77a1c8481313c259c3f3dd1d8379863 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13870 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08mainboard/skylake: Include WRDD method in WIFI ACPI deviceDuncan Laurie
Include the code to add the WRDD method to the existing WiFi Device in the mainboard ACPI code. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Compile for the other platforms that are modified. Change-Id: Ibcff7585744071ba9018d0ba50e274e63365b150 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b74bb553415f7ce224ddcb0c2c5ae509b8fed516 Original-Change-Id: Ieb24e0e64974ee3686d14a234e148f5d07fc8b12 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329296 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13840 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08soc/intel/quark: Set the UPD values for MemoryInitLee Leahy
Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13896 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-08soc/intel/apollolake: Add support for memory-mapped boot mediaAndrey Petrov
On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-07mainboard/intel/galileo: Enable SD flash cardsLee Leahy
Turn on the SD controller to allow it to claim resources. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when at the UEFI shell prompt: * After issuing: * "connect -r" * "map -r" * The "dir" command displays the contents of the SD flash card * The "drivers" command shows an SD host and SD media connection Change-Id: I883dc87270045786ddb931bea83fc36646a128e6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-01Skylake boards: Enabling HWP (hardware P state control)Subrata Banik
This patch provides config options to enable/disable Intel SST (Speed Shift Technology). BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: https://review.coreboot.org/13843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29mainboard/intel/galileo: Enable USBLee Leahy
Enable the EHCI and OHCI controllers. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when at the UEFI shell prompt: * After issuing: * "connect -r" * "map -r" * The "dir" command displays the contents of the USB flash drive * A USB keyboard can issue shell commands * The "drivers" command shows an EHCI and OHCI connection Change-Id: Iad9abced98d9b645e8b12fa0845c97260cf62a72 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13857 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-26mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init()Aaron Durbin
Now that the SoC is configuring the UART pads there's no need to implement bootblock_mainboard_early_init(). Remove it and bootblock.c. Change-Id: I2ae7ea38351733e1c9757cde20b79e1d19d0c1e5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13794 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-23southbridge/intel/lynxpoint: Use common gpio.cPatrick Rudolph
Use shared gpio code from common folder, except for INTEL_LYNXPOINT_LP, which has it's own gpio code. Needs test on real hardware ! Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13615 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-22mainboard/intel/galileo: Enable minimal ACPI tablesLee Leahy
Enable the minimal ACPI tables. Initialize the FADT header and provide an empty DSDT. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful if: * Outputs multiple lines of debug serial text Change-Id: I2e30c8af2994c9f56d9ba4fe6bc35e133b1d2d6b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13759 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18soc/intel/quark: Enable HSUART1Lee Leahy
Enable HSUART1 for debug serial output. Specify the fixed resources in the UART driver. This keeps debug serial output flowing during the rest of the device initialization. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * Debug serial output stays enabled after BS_DEV_RESOURCES state Change-Id: Ica02e5fece156b21d4a3889284ca467d55c7880d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13730 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18intel/kunimitsu: Set USB Type A current limit to 2ANaresh G Solanki
The GPIO USB_A0_ILIM_SEL & USB_A1_ILIM_SEL should be low to enable 2A charging from the USB Type-A port. BUG=chrome-os-partner:50212 BRANCH=glados TEST=Build CB & booted kunimitsu, verified that USB_A0_ILIM_SEL & USB_A0_ILIM_SEL are at logic zero. Change-Id: I989987eaaa2015720bbb1403caf20b97a996e168 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 640834506ad749359104e24fdb664044d499fd5f Original-Change-Id: I741f79a69b78dbb7d4f8cb9718355d802b94b96d Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327121 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13722 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-18southbridge/intel/bd82x6x: Use common gpio.cPatrick Rudolph
Use shared gpio code from common folder. Bd82x6x's gpio.c and gpio.h is used by other southbridges as well and will be removed once it is unused. Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-17mainboard/intel/galileo: Enable PCIe root port 0Lee Leahy
Enable PCIe root port 0 Testing on Galileo: * Add a 802.11 wireless card in the mini-PCIe slot * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing successful if: * After PCI 00:17.0, memory addresses are assigned to the 802.11 wireless card on PCI 01:00.0 during BS_DEV_RESOURCES state Change-Id: I68ea25b8e594480fe5146ffad75e293e346e9517 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13723 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-17mainboard/intel/galileo: Disable the remaining PCI devicesLee Leahy
Add additional lines to the devicetree.cb file to disable the PCI devices in the Quark SoC. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12emeraldlake2: Support native raminit.Vladimir Serbinenko
Change-Id: I808a739c91cb52782db46fd4897b6b913224d93f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13666 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2016-02-12chromebooks: Define GBB hardware IDsPatrick Georgi
This makes the test IDs the default, taken from depthcharge master (board/*/fmap.dts, hwid property). Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13634 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12Move gpio.h to gpio.c on sandy and ivy.Vladimir Serbinenko
Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13657 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13656 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-11soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLEAndrey Petrov
Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11mainboard/intel: Add skeleton for Apollolake RVP board familyAlexandru Gagniuc
RVP1 board comes with DDR3 SODIMMs and discrete VRs. RVP2 board uses LPDDR3 and PMIC. Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13298 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-09chromebooks: Configure Chrome EC board namesPatrick Georgi
For devices with Chrome EC, state the "board" name(s), so they're built as part of the image. A number of EC boards aren't supported in the Chrome EC master branch, they're brought along but commented out, waiting for a port to master in the Chrome EC code base. Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09intel/kunimitsu: Clean up GPIOs.Pratik Prajapati
Some of the pins are not connected/used on kunimitsu board, this patch will make them "Not connected". Un-used PINS will controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. BRANCH=none BUG=none TEST=Build and booted in kunimitsu. Change-Id: Iaf0d4806836648808fb91cfc7807c4c1595a5167 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7c25ad8ee0d189178124cff20569152b1053488 Original-Change-Id: I3add625b2bf01223cd389c6a5585827ac62dd0c0 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316700 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/13629 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09mb/intel/d510mo: Explicitly select NIC on PCI in devicetreeDamien Zammit
While the board configuration still works without this, It's nicer to have the device statically defined since the NIC is hardwired to the board. Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13455 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09skylake mainboards: Enable backing up VBNV from CMOS to flashDuncan Laurie
Enable the option to back up Vboot non-volatile data from CMOS to flash as these boards have the necessary nvram fmap region and are using vboot2 which does not backup to the TPM. BUG=chrome-os-partner:47915 BRANCH=glados TEST=manually tested on chell Change-Id: I7bfe88f2cb7826f3315987aaf56f77df708896ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35df03c5ef24406129cba920ee9af6d55458cd45 Original-Change-Id: Ia7c014fe2768c55941a65ec5605ef4fbc986151c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324123 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13601 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09intel/kunimitisu: set oem_id oem_table_id fields of acpi_header_tFang, Yang A
kunimitisu platform updated these two fields if maxim codec is detected. BUG=chrome-os-partner:49570 BRANCH=glados TEST=Build & Booted kunimitsu board. Verified that kernel can read new strings. Change-Id: Icbe0d87f0b46da794db36191b0e12948fe6a2fe6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f3d07ef07c382a2df140b457273feb3899228e10 Original-Change-Id: Ia6a111d15b851ae3fa918816e13b54ace215a09a Original-Signed-off-by: Fang, Yang A <yang.a.fang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/324631 Original-Commit-Ready: Yang Fang <yang.a.fang@intel.com> Original-Tested-by: Yang Fang <yang.a.fang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13603 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05mainboard/intel/galileo: Add board_info.txtLee Leahy
Add missing file to fix complaints by git commit script. TEST=None Change-Id: I4aac63821a7208fb86fa6c0dda16b7537e49a69a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04mainboard/intel/galileo: Add Intel Galileo Gen 2 SupportLee Leahy
Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Galileo Gen 2 board. Testing is successful if build completes successfully. TEST=Build for Galileo Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13507 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04skylake boards: disable ACPI PM TimerArchana Patni
These devicetree patches set the ACPI PM Disabled variable to 1. This will disable the ACPI PM timer and remove from FADT table. BRANCH=none BUG=chrome-os-partner:48646 TEST=Build for skylake board with the PmTimerDisabled policy in devicetree set to 1. iotools mmio_read32 0xfe0000fc should return 0x2. cat /sys/devices/system/clocksource/clocksource0/available_clocksource should list only "tsc hpet". acpi_pm should be removed from this list. Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319362 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04intel/kunimitsu: perform early init for CAR *stageAaron Durbin
In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=Built kunimitsu w/ separate verstage. Change-Id: If34cae5516a6df7f72f1f57cab495db70787177e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 543155665e1b05efe82c7440c124a5c83c656aa6 Original-Change-Id: I7281c4373fcbaaf0beedaa63dcf0dedb5316349f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324074 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13584 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02src/: Fix Kcofig symbols missing CONFIG_ prefixMartin Roth
- Add CONFIG_ prefix to two symbols. - Remove the use of the third symbol as it will never be matched. Change-Id: Ifa7f6884001cb05fb8397f193c4b08a0161f498c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13539 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-29src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig filesMartin Roth
Some trivial cleanup. Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-28intel/strago: Update DPTF parameters to higher temperature.Divagar Mohandass
Fish bowl HTML5 graphics benchmark with 250 fish is not reaching 60 FPS. This change will update the DPTF parameters to accommodate this test. TEST=Run fish bowl benchmark with 250 fish and check for 60 FPS. Change-Id: I6b6827199cb0f5ab44c354abc477ea73e4de9ec5 Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302208 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Fix for Crossystem "wpsw_cur" statusKumar, Gomathi
The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error.Original offset was 0x16 whereas it should be 0x13 TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291572 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-on: https://review.coreboot.org/13424 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Get Boot Flash Write Protect statusHannah Williams
Read GPIO to get the status Change-Id: Id2d56ce4b47c4cccba2de3f113afaee6c49885c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13186 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Braswell: Separate L1 Sub State init procedure for boards.Kenji Chen
Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: https://review.coreboot.org/12750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Strago: Enable CA MirrorShobhit Srivastava
Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is enabled on this board CQ-DEPEND=CL:13038 Original-Reviewed-on: https://chromium-review.googlesource.com/309190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12749 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28Strago: Disable SD Card Detect Simulation in FSPHannah Williams
CQ-DEPEND=CL:12742 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624 Reviewed-on: https://review.coreboot.org/13035 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Remove support for older rev boardsHannah Williams
Cleaning up code to remove support for early revs of Strago board Change-Id: Ic0647a17d78164fd7dfadc731c9395a8ba08c235 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13434 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Configure Boot Flash Write Protect status GPIOHannah Williams
Set up the GPIO(MF_ISH_GPIO_4) to read WP status. TEST=Use crossystem to read the WP status Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I17cbcba013e2a11c2527731df985aa1243065eff Original-Reviewed-on: https://chromium-review.googlesource.com/302424 Original-Tested-by: John Zhao <john.zhao@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13185 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Enable native mode on sd card cd lineJagadish Krishnamoorthy
Configuring Native Mode enables the card present bit in sd card controller register. TEST=Sd Card Plug/Unplug should work in OS and DepthCharge. Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12741 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Disable unused lines on Gpio North BankJagadish Krishnamoorthy
The unused lines leads to spurious interrupts on few of the systems. TEST=run suspend_stress test and make sure that kbd is working. Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313417 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13176 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28soc/braswell: Fix DSP clockfdurairx
The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com> Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28mb/intel/d510mo: Use SATA AHCI by defaultDamien Zammit
Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13454 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-01-28mb/intel/d510mo: Use native gfx initializationDamien Zammit
Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13034 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-28mb/intel/d510mo: Add CPU, SMI-trap and PIC to DSDTDamien Zammit
Change-Id: I80853cadb4762d9bb34926e31d65d248c5683417 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13453 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-28mb/intel/d510mo: Add missing GPIO and GPENDamien Zammit
Change-Id: I56c0a55d57d8beabcb33cf1984b037556a71a8b9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13452 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-28nb/intel/pineview: Native VGA init (CRT)Damien Zammit
VGA grub console works but display wobbles left/right drm/i915 driver reports one error: - [drm:i915_irq_handler] *ERROR* pipe A underrun - Monitor does not display 1920x1080 after modeset - Other resolutions look out of sync Cause: suspect single bug in raminit (chipset init) Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12921 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue.Kane Chen
LPC_CLKRUNB pin needs to be set to PU_20K to prevent leakage TEST=Test on Strago and make sure the leakage is gone Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: Id2bf7511806cdc52b505bb469238a9465b356352 Original-Reviewed-on: https://chromium-review.googlesource.com/317020 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13175 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 03:52:20 +0000