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2018-08-25mb/intel/coffeelake_rvp: Remove superfluous header fileArthur Heymans
TEST: same sha256sum with BUILD_TIMELESS=1. Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-08-22src/mainboard/*: Remove IFD_*_REGION values for ifdfakeAngel Pons
Since ifdfake has been deprecated in favor of better alternatives, such as flashrom IFD parsing. Therefore, there is no need to support ifdfake any further. Remove the IFD_*_REGION values on the few motherboards with them. Change-Id: Ie07116a7fb960c6ca832d802016f22c6677baac9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28232 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-21nb/intel/pineview: Use a common MMCONF_BASE_ADDRESSArthur Heymans
This should not be board specific. Change-Id: Ifa617e84af767f33a94f1ddfa7d4883c1a45198f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20soc/intel/common/block: Move common uart function to block/uartSubrata Banik
This patch moves uart functions which are common across multiple soc to block/uart. This will remove redundant code copy from soc {skylake/apollolake/cannonlake}. BUG=b:78109109 BRANCH=none TEST=Build and boot on KBL/APL/CNL platform. Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-17mb/intel/coffeelake_rvp: Update spd details as per Coffeelake boardMaulik V Vaghela
Update SPD details to match with Coffeelake U RVP board BUG=none BRANCH=none TEST=Boot on coffelake U rvp board and check if memory training is passing and board boots till payload. Change-Id: I953354cf5c6045731262f4f4e9da230187c2d246 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-17mb/intel/coffeelake_rvp: Update GPIO table for Coffeelake U RVPMaulik V Vaghela
Update GPIO table as per board schematics. GPIO table for other variants will be added later. Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-08-15mb/*/*/cmos.default: Decrease debug_level to 'Debug'Elyes HAOUAS
Used default console log level is 7 in src/console/Kconfig. So let cmos.default use the same level as default. Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-14src: Remove duplicated 'include <device/device.h>'Elyes HAOUAS
Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-14mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake UMaulik V Vaghela
Coffeelake U has 32MB flash chip support. Adding fmd file and enabling CFL U board's Kconfig to output 32MB rom file. Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-08-14mb/intel/coffeelake_rvp: Add support for new board coffeelake RVPMaulik V Vaghela
Add support for new board coffeelake RVP. This patch is a copy patch and copies entire coffeelake_rvp folder from cannonlake_rvp. Changes done on top of copy: 1. Change copyright year from 2017 to 2018 2. Rename Cannonlake to Coffelake whenever applicable 3. Update entries in Kconfig and Kconfig.name 4. Rename variant directories to match coffeelake boards Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27904 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/intel/cannonlake_rvp/Kconfig: Don't redefine firmware pathsArthur Heymans
The paths defined in southbridge/intel/common/firmware/Kconfig should work just fine. Change-Id: Iaa780d9b3080416c6b1a7f24d97ecb8214962405 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28012 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13soc/intel/broadwell/Kconfig: Clean up redefined config optionsArthur Heymans
All broadwell board set HAVE_IFD_BIN to default n, overloading the option in soc, therefore just use the defaults in sb/intel/common/firmware. Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28011 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13sb/intel/lynxpoint/Kconfig: Clean up redefined config optionsArthur Heymans
There is no need to redefine option present in southbridge/intel/common/firmware/Kconfig. Change-Id: I9999440031b07006e2df11e00dfb9f3dbe04f832 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28007 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13fsp_broadwell_de: Increase CONFIG_MAX_CPUS to 32Samuel Jimenez
Fix to accomodate for boards with more than 16 cores. Change-Id: I35b61d94491c21ef76717f761e566ca815880f27 Signed-off-by: Samuel Jimenez <aerojsam@gmail.com> Reviewed-on: https://review.coreboot.org/27847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13src/mb: Remove some unneeded includesElyes HAOUAS
Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13mb: Get rid of unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I80dd65484fd52e9048635091fb20a123e959e999 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27869 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/intel/dg43gt: Enable the GBEArthur Heymans
This was blindly copied from logs created under vendor BIOS in non-descriptor mode which apparently set LAND in BUC. Change-Id: I94c917600421ee742ece7f6f71309da80261da28 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-09src/mainboard: Fix typoElyes HAOUAS
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08mb/intel/cannonlake_rvp/devicetree: Remove spurious CPP directivesArthur Heymans
The devicetree is not run through a C pre-processor, so remove it. Change-Id: I161be45b2035f3a8724bf3217260e7571c429da8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27927 Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-05southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by defaultAngel Pons
Since only a handful of boards have descriptor blobs in the tree, it makes no sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard. This patch flips the default value of said variable, rendering all current overrides unnecessary. The few boards which have an IFD in the blobs repo use `select HAVE_IFD_BIN` to enable adding the IFD by default. Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed alongside the latter, and has been added to the boards with a ME blob as `select HAVE_ME_BIN`. Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well. Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06mb/intel/d945gclf/romstage.c: Remove unneeded includesElyes HAOUAS
Change-Id: I3bdb93e51cabbfc14fe992ccdb6556e344e03c2f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-03mb/intel/dg43gt: Expose some SIO devices via ACPIArthur Heymans
Change-Id: I0df578b98c5b346caa6f6df5fdabda28788e6b66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-03mb/intel/dg41wv: Expose some SIO devices via ACPIArthur Heymans
Change-Id: Ia658c117434c3fae45bbbe6c472ca58ba4f1a117 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-03mb/intel/glkrvp: Get rid of DRIVERS_PS2_KEYBOARD selectionFurquan Shaikh
Until now, chromeec was doing keyboard initialization for the boards that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not leave the keyboard controller in a default reset state. This could result in payloads or OS failing to probe the controller as there could be stale data buffered in the controller during the handoff. Since the boards using chromeec already perform keyboard initialization in payload, there is no need to initialize the keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD selection from all google mainboards using chromeec. BUG=b:110024487 Change-Id: I9af48e648231c18f98d0cc1ddd178b8d00082b0a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-02src/mb: Fix non-local header treated as localElyes HAOUAS
Also remove some unnedded includes. Change-Id: I036208a111d009620d8354fa9c97688eb4e872ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28mb/*/*/cmos.layout: Fix coding styleElyes HAOUAS
Change-Id: I4f82482595b0e6c6159c6e1c66158bc18b061f04 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-22soc/intel/common/block/cpu: Add option to skip coreboot AP initSubrata Banik
SoC users from IOTG team is looking forward for a solution to skip coreboot AP initialization flow and make use of FSPS-UPD to perform AP reset. TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs out of reset. Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-15soc/intel/{glk,apl} and mainboards: Configure LPC_CLKRUN# pin as GPIO for S0ixHannah Williams
This pin does not have a native function for eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO and kept unconnected to allow S0ix entry. Also removed initialization of LPC pins in mainboard code as they are already initialized in chipset code. The settings fpr LPC pins in chipset code were updated to those that were previously in mainboard code and have been validated on LPC flavor of Geminilake RVP. BUG=b:79251613 BRANCH=none TEST=From kernel prompt in bip, type powerd_dbus_suspend. Check on EC console that SOC enters S0ix. Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23742 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
Tested on Google peppy (Acer C720). Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14mb/*/*: Enable libgfxinit on x4x boardsArthur Heymans
TESTED Intel DG41WV with VGA, Intel DG43GT with VGA and HDMI1 and HDMI2. Change-Id: I774b79cc0ef9dc72ccf48901ab94376b27ed9c7a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12drivers/intel/gma: Unify VBT related Kconfig namesNico Huber
Shuffle words and drop the _DATA_FILE suffix. Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-11mb/*/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: If1f032d097224a1102ba29d8d45dce46aad3a91a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-09mainboard: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage. Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26984 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-09mainboard: Get rid of device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06mb/*/*: Add a few VBT filesArthur Heymans
These files are directly extracted from the vendor firmware. Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05soc/intel/cannonlake: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization for CNL. Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05soc/intel/skylake: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization. Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04mb/intel: Get rid of whitespace before tabElyes HAOUAS
Change-Id: I891b056b64fde27ef0e351f8cf24a258fb5cabfa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-03intel bd82x6x/lynxpoint systems: Update ACPI thermal zone handlerMartin Roth
Currently the throttle event handler method THRM is defined as an extern on the intel bd82x6x and lynxpoint chipsets, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. This also requires moving the thermal handler, which now includes the define to before the gnvs asl file. TEST=Build before and after, make sure correct code is included. Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26123 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDENico Huber
As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-26mainboard/intel/dg41wv: Fix lint check errorMaulik V Vaghela
Fix lint error due to non-ASCII characters BUG=none BRANCH=none TEST=check if no error in checkpatch.pl script. Change-Id: Iec7682e460c8e0d467a70349a23390554cc1de92 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26562 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-26mb/intel/dg41wv: Add mainboardArthur Heymans
This board was used a test target for the x4x DDR3 raminit patches and has an easy to access DIP8 socket. What is tested and works: * S3 resume * PEG, PCI, USB, SATA * Sound * Ethernet * Native graphic init (textmode and linear fb) on the VGA output * Passing memtest86+ with 2 2Rx8 4G dimms * PS2 Keyboard * Flashing coreboot internally from vendor BIOS. What does not work: * Running dram at 533 MHz (limited at 400MHz currently) Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux 4.10. Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20003 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 12:23:36 +0000