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2018-05-01nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans
This change also makes sure that the sum the uma regions (TSEG, GSM, GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between 2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR setup for ramstage. At least tianocore requires this and fails to boot without it. Better MTRR are achieved by making the memory 'hole' till 4GiB exactly 2Gib. This code mimics how it is done in nb/intel/gm45 and achieves similar results. TSEG is enabled and set to 8M since this makes it easier to reuse the common smm setup / parallel mp code and makes it possible to cache the ramstage in there like how it's done on newer targets. TESTED on Intel DG43GT. Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-11mainboard/intel/cannonlake_rvp: include correct SND related DT entriesSathyanarayana Nujella
For cannonlake_rvp, want to support two sound configurations based on relevant daughter board connected (either of these configurations: SND_MAX98373_NHLT and SND_MAX98357_DA7219_NHLT). By default SSDT included all codec entries. This patch corrects and includes relevant codec entries in SSDT BUG=None BRANCH=master TEST=Verify 'emerge-cnlrvp coreboot' compiles successfully. Change-Id: I4f9487f3a81ef2d24315f75ec1d34bfab8560224 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/24918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11mb/intel/dg43gt/devicetree.cb: Use tabs over spacesElyes HAOUAS
Change-Id: I5d18dfea0b0a33995de805219bda3a73892e5fde Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-06mb/intel/glkrvp: Unselect Chrome EC specific config when using Intel ECNaresh G Solanki
When building with Intel EC selected, unselect Chrome EC specific options i.e., LID switch to prevent build error. BUG=None BRANCH=None TEST=Build with Intel EC selected, Build should be successful. Change-Id: I39d6d65bbfd08d684af43972b89ca78fcbd58567 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25479 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28mb/intel/glkrvp: Enable ThunderPeak wifi cardRoy Mingi Park
This enables ThunderPeak WiFi card on M.2. TEST=Verify wlan card shows up in lspci Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/24931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-25mb/glkrvp: Set PNP config to PNP_PERF_POWERShaunak Saha
This patch sets the PNP config value to PNP_PERF_POWER. The config values for soc can be found in chip.h TEST = Built and booted glkrvp, verified warm and cold reboot and suspend resume. Change-Id: Ia390c0fafe2de64bd9e4ca44e5ed5d904663ae3c Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-23mainboard/intel/cannonlake_rvp: Enable S0ixVaibhav Shankar
This patch enables S0ix from the devicetree. Change-Id: I38662dc7203366bdee5f1c7aaa18979867a79ba1 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/25293 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23mb/intel/kblrvp8: Add KBLRVP8 supportV Sowmya
Add the config for setting SPD DIMM size to 512 bytes for KBLRVP8 with DDR4 memory. Configure the DIMM1 memory SPD data for channel0 and channel1. Set the UserBd UPD to BOARD_TYPE_DESKTOP for kblrvp8. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 Reviewed-on: https://review.coreboot.org/25194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-03-21mb/intel/glkrvp: Re-size flash WP_RO segmentSrinidhi N Kaushik
Update the size in WP_RO segment of the flash to accommodate builds using debug FSP. Change-Id: I8b24422e1eef2d0a81006286d4fc58f238fdce11 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-16soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin arrayFurquan Shaikh
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-15mb/intel/glkrvp: Add FPF_STATUS section in fmd fileHannah Williams
Read cse file was not getting cached and taking about 500ms on every boot. Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-14mb/*/spd: Use normal binary numbers (0b0010) instead of special format (2b0010)Jonathan Neuschäfer
This format (one hex digit, followed by 'b', followed by binary digits) is arguably useful, but also confusing. Use the more common format instead. Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-08mb/intel/kblrvp: Enable Kabylake RVP8V Sowmya
Add support for KBL RVP8 board * Add KBL RVP8 support in Konfig. * Add KBL RVP8 config option in make menuconfig. * Add descriptor and ME binary paths for RVP8 in Kconfig. * Add RVP8 board name Kconfig.name. * Add devicetree.cb for RVP8 in the variants path. * Add gpio.h for RVP8 in variants/include/variant path. TEST= Build and boot RVP8. Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23383 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-05mb/intel/glkrvp: Set S0ix lazy wake maskShamile Khan
Enable S0ix wake mask programming from coreboot using unified host event programming interface. BRANCH=none BUG=none TEST=Verify masks with ec hostevent command on S0, S3, S5 and S0ix. Also check that lidclose/lidopen command from EC console wakes system up from S3 or S0ix. Change-Id: I60343aaa9e0ddfd38d42b6d0aa2820e2fd880fb7 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23453 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driverSubrata Banik
Now SOC code can select the require UDK support package for any platform going forward with FSP2.0 model. Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25mb/intel/glkrvp: Select SOC_ESPI to enable eSPIShaunak Saha
Add config option SOC_ESPI in glkrvp Kconfig. This is to disable LPC and enable eSPI instead. TEST=Boot to OS Change-Id: I3116b656d41d1d7719c254888d1e3640628a97ca Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-24mainboard/intel/cannonlake_rvp: remove redundant settingLijian Zhao
Clean up the extra DRIVERS_I2C_GENERIC BUG=None TEST=None Change-Id: Ida32b6f99c40c022aa8548f7353abf1d60ba4ddf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mainboard/glkrvp: Ignore DMIC_DATA pin IOSSTATERavi Sarawadi
Audio DMIC_DATA needs to be ON in S0ix to support Wake on Voice. By doing this, SoC can see the DMIC DATA and use for WoV processing. Thus configuring GPIO_173 as IGNORE IOSSTATE. TEST=put DUT in S0ix, verify DUT wakes up Change-Id: I8bf403564e927deb8fed7f415e334bb230107cb0 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23246 Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
Most affected boards set the function disabled (FD) register to an arbitrary state dumped from systems running the vendor BIOS. This makes it impossible to enable the devices in devicetree and a pretty big mess of course because nobody cared to keep the register in sync with the devicetree. To get completely rid of most of the writes to FD, move setting of PCH_DISABLE_ALWAYS into the southbridge code where it belongs. Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-23mainboard/intel/cannonlake_rvp: Add support for MAX98373 speaker ampN, Harshapriya
Add NHLT and dt support for max98373 amp BUG=None TEST=check SSDT and verify entries for max98373 TEST=check NHLT ACPI tables included blobs for max98373 Change-Id: I0b402f89f1ece9e62a394f713c4b0feff29bd1e5 Signed-off-by: N, Harshapriya <harshapriya.n@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/22674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mainboard/intel/cannonlake_rvp: Add support for SND_MAX98357_DA7219Lijian Zhao
Add NHLT and dt support for Audio with Max98357 and DA7219 TEST=verified NHLT tables and SSDT entries BUG=None Change-Id: If7960eb6bb441f35cbd9a8a6acc37f03e04e3b70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/22144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-18Intel i82810 boards & chips: Remove - using LATE_CBMEM_INITKyösti Mälkki
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i82810 Mainboards: src/mainboard/asus/mew-am src/mainboard/asus/mew-vm src/mainboard/ecs/p6iwp-fe src/mainboard/hp/e_vectra_p2706t src/mainboard/intel/d810e2cb src/mainboard/mitac/6513wu src/mainboard/msi/ms6178 src/mainboard/nec/powermate2000 Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23300 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17cpu/intel/speedstep: Fix the PNOT ACPI methodArthur Heymans
The PNOT method never notifies the CPU to update it's _CST methods due to reliance on inexisting variable (PDCx). Add a method in the speedstep ssdt generator to notify all available CPU nodes and hook this up in this file. The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now relies on code generated in the speedstep ssdt generator. CPUs not using the speedstep code never included this PNOT method so this is a logical place for this code to be. Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15Intel i3100 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-14mb/*/*/romstage.c: Clean up targets with i82801gxArthur Heymans
Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-12mainboard/glkrvp: Add EC_GOOGLE_CHROMEEC_SWITCHESShaunak Saha
This patch adds the EC_GOOGLE_CHROMEEC_SWITCHES option so that we use the common switch.c file Change-Id: I93a2ba63015db17989c89ce1b5897de6a93e201f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mainboard/glkrvp: Add RECOVERY_CACHESrinidhi N Kaushik
This patch adds recovery cache. TEST:glkrvp boots with this change and also FAFT test firmware_CorruptRecoveryCache passes. Change-Id: I9b32628d814693fb0591fc3750348d48cf9e26f1 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/23067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mb/intel/kblrvp: Use common HDA codeDuncan Laurie
Instead of duplicating code in each mainboard that supports HDA use the common driver and provide the HDA verb table. This was compile tested for both variants with "abuild -t intel/kblrvp" Change-Id: Ie3bab7aabcfa040935062b7764853df8fb19b04d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-07intel/dcp847ske: Add superio ACPI declarationsTobias Diedrich
Tested on Linux 4.13.14: SuperIO resources show up as reserved in /proc/ioports and friends. Change-Id: I0363816fe048579413f1325dcfc9a6a8a9e48123 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-05nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeoutArthur Heymans
Especially on ICH7 failing to do so results in i2c block read being unusable. On ICH10 this problem doesn't manifest itself that much. This moves disabling the watchdog reboot to the northbridge code like i945 (even though it technically is southbridge stuff). TESTED on Intel DG41WV: hacking on raminit is much nicer since no need to do a hard power down for +4s are needed to clear the timeouts. Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-12-22mb/intel/dcp847ske: remove reference to non-existent fileAaron Durbin
In commit 7a95204 (intel/dcp847ske: Add Intel NUC DCP847SKE) the default_irq_route.asl file was removed, but this mainboard was missed. Follow suit with the original intent of the commit and fix the build breakage. Change-Id: I909dad7cfc0fab37e29187b2358f7f056216a403 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22975 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-22intel/dcp847ske: Add Intel NUC DCP847SKETobias Diedrich
https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE Created using autoport and manual edits. mainboard_fill_pei_data copied and adjusted from samsung/lumpy. Tested: - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V). - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V). - SeaBIOS stable payload. - Linux 4.13.14 payload. - Booting into Linux 4.13.14 with Debian/unstable installed on the internal mSATA slot. - Non-native raminit (works). - Native raminit - KVR1333D3S9 doesn't work. - KVR16LS11 only works at 1.5V. - Native VGA init, HDMI port detection with libgfxinit. - Basic ACPI functions (power button event; power-off; reboot). - Suspend to RAM and resume works. - PCIe WLAN in half-minicard slot. - USB device in half-minicard slot. - PCIe device in full-minicard slot. - mSATA device in full-minicard slot. - Fan spins up/down in response to CPU load. Known issues: - Native raminit fails timC calibration with the RAM I have. - Technical Product Specification mentions overcurrent protection for back panel and front panel USB connectors, but I haven't been able to trigger it with either native fw or coreboot (tried up to 2.5A load). Untested: - USB debug port. Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-22soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion supportDivya Chellap
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/intel/glkrvp: Configure SCI/SMI in glkrvp for ESPIShaunak Saha
This patch configures the EC_SCI_GPI when ESPI is enabled.Also adds mainboard espi handler function. TEST= Boot to OS and SMI/SCI is working when ESPI is enabled/disabled. Change-Id: I2b3845d54ad7c1f14edc86f71b3f968424711999 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20intel/bd82x6x: Use generated ACPI PIRQTobias Diedrich
Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 (sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X. This generates the main ACPI _PRT table automatically based on the chipset registers. Tested on Intel NUC DCP847SKE with Linux 4.13.14: $ cat /proc/interrupts CPU0 CPU1 0: 23 0 IO-APIC 2-edge timer 8: 1 0 IO-APIC 8-edge rtc0 9: 0 0 IO-APIC 9-fasteoi acpi 19: 86 0 IO-APIC 19-fasteoi ehci_hcd:usb1 23: 0 0 IO-APIC 23-fasteoi i801_smbus [...MSI and other interrupts skipped...] Log messages: ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6 ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4 ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4 ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8 ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1 Generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: I832a86925283d61b64b8268246d9e6f11994c120 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20mainboard/intel/cannonlake_rvp: Disable SATA controllerVaibhav Shankar
SATA was enabled only for internal testing. Since we do not use SATA on chrome platforms, it can be disabled. Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mainboard/intel/saddlebrook: add support for Saddle BrookTeo Boon Tiong
Add initial files to support the Saddle Brook board. This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. Most of the code has been taken carried over from kunimitsu with changes done for Saddle Brook. Saddle Brook is a reference board for Skylake SOC and has DDR4. TEST=Build with uefi payload and boot to Linux 4.9 on CRB successfully. Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e Signed-off-by: Anuj Mittal <anujx.mittal@intel.com> Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/21436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-12-14mainboard/intel/glkrvp: Configure Prmrr and Enable SGXPratik Prajapati
Configure PRMRR to allocate 128MiB for SGX enclave memory and enable SGX by default for GLKRVP platform. Supported PRMRR size options: 0x02000000 - 32MiB 0x04000000 - 64MiB 0x08000000 - 128MiB Change-Id: Ifa39df4a1da84bae49551a9626257bda0729752b Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-14mb/glkrvp: Enable TouchpadShaunak Saha
This patch enables the APLS touchpad in glkrvp platform. TEST= Boot and test touchpad works. Change-Id: I6f52f7db57ab52b5531e647bde2adbb78b40f76f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22627 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-13mb/cannonlake_rvp: Enable TouchpadShaunak Saha
This patch enables the APLS touchpad in cnl-y platform. TEST= Boot and test touchpad works. Change-Id: I461b9d119b1cac6c8c6cb9b096697f58e00d80ad Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22369 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-09mb/intel/glkrvp: Add gpio.h in dsdt.asl fileShaunak Saha
Add proper variants gpio.h in dsdt.asl where the GPE_EC_WAKE and EC_SCI_GPI is defined. Change-Id: Ideb6dd4d0ac496a81721cd883865218cb19583d9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08src/mainboard/glkrvp: Turn on CPU fanSrinidhi Kaushik
On GLK EC does not support temperature reads and does not control the fans anymore, OS is responsible fan control through EC. This hack enables running of the fan for boards without External EC. Change-Id: I361e53d4fd53678f3abb8fe9862071aec6e149a7 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/22235 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-12-08mb/intel/glkrvp: Fix CLKRUN gpioShaunak Saha
This patch does not put CLKRUN in IOSTANDBY. Change-Id: I7fedd729d3bb66c2b52a63166e461f8760457721 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-07mainboard/intel/glkrvp: Change gpio configuration for eSPIBora Guvendik
Skip LPC related gpio configuration if eSPI config option is selected. Change-Id: I15c5f769f36a1801217b1e3650379c7b181d814f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22757 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-20 04:11:48 +0000