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path: root/src/mainboard/intel
AgeCommit message (Expand)Author
2012-11-16Fix PIRQ routing abstractionStefan Reinauer
2012-11-16Fix Kconfig GENERATE_*_TABLE usageStefan Reinauer
2012-11-16Drop Kconfig variable BOARD_HAS_HARD_RESETStefan Reinauer
2012-11-16Drop unneeded BOARD_HAS_FADT optionStefan Reinauer
2012-11-16Reduce number of per-mainboard changesStefan Reinauer
2012-11-14Move HAVE_SMI_HANDLER from mainboards to chipsetsStefan Reinauer
2012-11-14SMM: Save the GNVS pointer when creating APCI tablesDuncan Laurie
2012-11-14SMM: Avoid use of global variables in SMI handlerDuncan Laurie
2012-11-13Make EmeraldLake2 work againDuncan Laurie
2012-11-12ACPI: Zero pstate/cstate control values in FADTDuncan Laurie
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
2012-11-06intel/socket_BGA956: enable speedstep, CAR, MMX, SSEPatrick Georgi
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
2012-10-08hpet: common ACPI generationPatrick Georgi
2012-10-05Use mainboard_interrupt_handlers everywherePatrick Georgi
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
2012-08-01Intel and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
2012-07-26Drop mainboard chip.hStefan Reinauer
2012-07-26Remove copies of rtl8168.cPatrick Georgi
2012-07-24ChromeOS: Remove board specific acpi_get_vdat_info()Stefan Reinauer
2012-07-24Drop (empty) sandybridge_late_initialization()Stefan Reinauer
2012-07-24Remove CMOS Extended range enable from romstageDuncan Laurie
2012-07-24Move GGL0001 ACPI code to generic ChromeOS codeStefan Reinauer
2012-05-26Move subsystem IDs to devicetree.cbStefan Reinauer
2012-05-08Clean up #ifsPatrick Georgi
2012-05-03Don't pre-enable SATA AHCI in romstage.cStefan Reinauer
2012-05-02ChromeOS: drop unused debug header descriptionStefan Reinauer
2012-05-01Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boardsStefan Reinauer
2012-05-01Clean up Emerald Lake 2 mainboard directoryGabe Black
2012-05-01Allow more CPU cores on Emerald Lake 2 CRBStefan Reinauer
2012-05-01Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.Gabe Black
2012-05-01Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer
2012-05-01Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.Gabe Black
2012-04-30Add support for Intel Emerald Lake 2 CRBStefan Reinauer
2012-04-27Move top level pc80 directory to drivers/Stefan Reinauer
2012-04-20Refactor some alignment handlingPatrick Georgi
2012-04-15cmos.layout: Remove invalid warningVikram Narayanan
2012-03-16Intel northbridge I945: Apply un-written naming rulesKyösti Mälkki
2012-03-08Unify Local APIC address definitionsPatrick Georgi
2012-02-24Ati video: Apply un-written naming rulesKyösti Mälkki
2012-02-22ACPI: More ../../.. removalPatrick Georgi
2012-02-17intel/i82801cx: Move HAVE_HARD_RESET to southbridgePatrick Georgi
2012-02-17intel/i82801ex: Move HAVE_HARD_RESET to southbridgePatrick Georgi
2012-02-10Intel cpus: apply un-written naming rulesKyösti Mälkki
2012-01-31northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig optionPeter Stuge
2011-12-02i3100: Add HAVE_HARD_RESETSven Schnelle
2011-10-30remove usbdebug.h include from mainboard/romstage codeSven Schnelle
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
2011-10-13Use default table creator macro for all SSDTsStefan Reinauer
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