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Some coreboot project code with my work
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iwave
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iWRainbowG6
Age
Commit message (
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Author
2012-11-14
Move HAVE_SMI_HANDLER from mainboards to chipsets
Stefan Reinauer
2012-11-06
Drop redundant CHIP_NAME in mainboard.c
Kyösti Mälkki
2012-10-26
iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned
Sebastian Andrzej Siewior
2012-10-26
iwave/iWRainbowG6: remove USE_DCACHE_RAM
Sebastian Andrzej Siewior
2012-10-08
hpet: common ACPI generation
Patrick Georgi
2012-08-08
Cleanup coreboot memory table includes
Kyösti Mälkki
2012-07-26
Drop mainboard chip.h
Stefan Reinauer
2012-04-20
Refactor some alignment handling
Patrick Georgi
2012-04-12
Unify IO APIC address specification
Patrick Georgi
2012-03-08
Unify Local APIC address definitions
Patrick Georgi
2012-02-22
ACPI: More ../../.. removal
Patrick Georgi
2012-02-17
intel/sch: Move HAVE_HARD_RESET to southbridge
Patrick Georgi
2011-10-13
Use default table creator macro for all SSDTs
Stefan Reinauer
2011-10-13
mptable: Refactor mptable generation some more
Patrick Georgi
2011-10-13
mptable: Get rid of fixup_virtual_wire
Patrick Georgi
2011-10-13
mptable: Refactor lintsrc generation
Patrick Georgi
2011-09-21
Use ACPI text fields consistently with all other boards
Stefan Reinauer
2011-08-26
Add automatic SMBIOS table generation
Sven Schnelle
2011-06-07
SMM: add defines for APM_CNT register
Sven Schnelle
2011-05-23
AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards.
Stefan Reinauer
2011-04-22
The UART divider should be calculated based on the base frequency
Stefan Reinauer
2011-04-20
run uart_init() from console_init, just like the other console initialization...
Stefan Reinauer
2011-01-27
oops. this is weird. CAR addresses should be specified in the socket and not in
Stefan Reinauer
2010-12-18
Fix a few whitespace and coding style issues.
Uwe Hermann
2010-12-18
A couple of Poulsbo fixes:
Patrick Georgi
2010-12-18
Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
Patrick Georgi