coreboot - Some coreboot project code with my work

Age	Commit message (Collapse)	Author
2014-07-18	mainboard: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
	Change-Id: If29a70be4fb56ebb0dbf6d510412cbe2f34480ef Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6291 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-03	Move ARCH_* from board/Kconfig to cpu or soc Kconfig.	Furquan Shaikh
	CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26	superio/fintek/*: Factor out generic romstage component	Edward O'Callaghan
	The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-02	superio/fintek/f71805f: Avoid .c includes	Edward O'Callaghan
	Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5434 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19	board-status: Add board_info.txt extracted from wiki.	Vladimir Serbinenko
	board_info.txt is a file to be used by board-status to add some useful info to the generated table like flash chip type. This series is autogenerated from wiki page Supported_Motherboards. Change-Id: Ie2bda900713ef4883134477163320936c84c34f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4701 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19	jetway/j7f4k1g2e and jetway/j7f4k1g5d: Add as clones of jetway/j7f2.	Vladimir Serbinenko
	Change-Id: I16e027b78dc65538d8f0cd6f5e57bbdfc10b7169 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4729 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-19	jetway/j7f24: Rename to jetway/j7f2.	Vladimir Serbinenko
	Original actually meant j7f[24] which without square brackets became confusing. There is no such board as j7f24. This is a prerequisite to adding j7f4* as cloned boards Change-Id: Ia7708b13ac4141ef788183c7817fce1366919936 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4728 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)