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2013-11-24smi: Update mainboard_smi_gpi() to have 32bit argumentDuncan Laurie
With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4145 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-10-14Revert "CBMEM: Always have early initialisation"Kyösti Mälkki
This reverts commit de1fe7f655c549e8dce5b34218221890fa5ccc34. While things appeared to work, there were actually invalid references to CAR storage after CAR was torn down on boards without EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be restricted to boards that handle CAR migration properly. Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21CBMEM: Always select CAR_MIGRATIONKyösti Mälkki
If romstage does not make cbmem_initialize() call, linker should optimize the code for CAR migration away. This simplifies design of CBMEM console by a considerable amount. As console buffer is now migrated within cbmem_initialize() call there is no longer need for cbmemc_reinit() call made at end of romstage. Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21CBMEM: Always have early initialisationKyösti Mälkki
Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig. If romstage does not make the cbmem_initialize() call, features like COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during romstage, but that data will get lost as no CAR migration is executed. Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3917 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps: Stash early timestamps in CAR_GLOBALKyösti Mälkki
Change-Id: I87b454c748cf885491d5b38bfe53a2ec0e9f38c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3910 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps intel: Move timestamp scratchpad to chipsetKyösti Mälkki
This retrieves back the value stored with store_initial_timestamp() in the bootblock for southbridge. Change-Id: I377c823706c33ed65af023d20d2e4323edd31199 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3908 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Drop parameter from cbmem_reinit()Kyösti Mälkki
Function is always called with get_top_of_ram() - HIGH_MEMORY_SIZE which equals cbmem_base, thus no need to pass it as a parameter. Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29kontron/ktqm77: Allow disabling onboard NICsPatrick Georgi
Two new nvram variables control disabling the two non-ME NICs on the mainboard. This is implemented by disabling their PCIe bridge. Change-Id: I086f0d79de3ad0b53fa0ec40648d63378070e3bd Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3870 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-28kontron/ktqm77: Drop MRC_FILE definitionPatrick Georgi
The northbridge defines it already and to the same value. Change-Id: Ia5d856258fac52ea0b249142f70a89123ca04f82 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/3876 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-16Correct spelling of shadow, setting and memoryPaul Menzel
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16kontron/ktqm77: Update MRC pathPatrick Georgi
It still pointed to the old binary despite implementing the newer interface Change-Id: Iebd5dae98168f5568f3ad6a18c5ebde9abc3ece0 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3869 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15Include boot_cpu.c for romstage buildsKyösti Mälkki
ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-07-31Drop unused EXTERNAL_MRC_BLOBStefan Reinauer
The Kconfig variable EXTERNAL_MRC_BLOB is not used. Drop it. Change-Id: I3caa5c2b6bcf5d2c13b6987da8ab3987bad0e506 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3829 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-29kontron/ktqm77: Update cmos checksum rangeNico Huber
Change-Id: I08e56b4a1c56128c6d4beb751979c5b99cdae829 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29kontron/ktqm77: Squeeze more fan options into cmos.layoutNico Huber
Change-Id: Ic660efec519a9a970ec5a8832fd1dd8c9516318f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3775 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04intel/i945: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Change all PCI configuration accesses to MMIO on all boards with i945 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-04intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Change all PCI configuration accesses to MMIO on all boards with SandyBridge and IvyBridge. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3576 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-25ktqm77: redesign cmos.layout slightlyPatrick Georgi
BIOS write protects 8 bytes of CMOS, which nvramtool can't cope with. This makes initial installation harder, so just mark those as reserved to work around the issue. Change-Id: I210861dff8572e226a0f250556a3b811671ea8f2 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3531 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24kontron/ktqm77: New boardNico Huber
Change-Id: Ife1c0a8597c2de04773899cdd87af6b6c630906a Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3392 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24AMD: Drop empty root_complexKyösti Mälkki
There are no files to build left under AMD nortbridge/x/root_complex directories. For some cases, even the Kconfig file was no longer sourced. Remove all such references and empty files. For devicetree.cb treat component paths with "/root_complex" in them valid even when the directory does not exists. This is because AMD boards us this dummy chip component as the root node in their devicetree.cb. The generated devicetree file static.c remains unchanged. Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-25mainboard.c: Name enable_dev function uniformly `mainboard_enable`Paul Menzel
To reduce the differences between these file name the enabling device function in the directory `src/mainboard` uniformly `mainboard_enable` [1]. Thanks to the awesome help of gnomon and BlastHardcheese in the IRC channel #sed on <irc.freenode.net>. gnomon came up with the following command to do the actual work. $ cd src/mainboard $ for f in */*/mainboard.c ; \ > do src="$(awk '/\.enable_dev = /{v=$NF; sub(/,$/,"",v); print v}' "$f")" ; \ > [[ -z $src ]] && continue ; \ > printf '%s\n' "g/${src}/s/${src}\([,(]\)/mainboard_enable\1/p" w | ed -s "$f" ; \ > done `src/mainboard/digitallogic/msm586seg/mainboard.c` and `src/mainboard/technologic/ts5300/mainboard.c` had to be adapted manually as no comma was used separating the struct members. And with the following statement, gnomon is even more likable! My pleasure entirely. Good luck with coreboot; I'm a big fan of the project. [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074548.html Change-Id: Ife9cd0c2d9cc1ed14afc6d40063450553f06a6c6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2493 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-04Intel based boards: Use tab instead of spaces to align comment in DSDTPaul Menzel
Mainboards using `COREBOOT` as their OEM Table ID in their DSDT header were copied from the same source and therefore had spaces instead of a tab to align that comment for that header field. These are mostly Intel based boards. Fix that in accordance with the coding style [1]. [1] http://www.coreboot.org/Development_Guidelines#Coding_Style Change-Id: I299b955930dbd50b9717e8ff141ce8f3fd534e5f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2277 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-01-03Rename mainboard_smi.c to smihandler.cPatrick Georgi
This mirrors the naming convention of handlers in northbridge and southbridge. Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2058 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-28amdk8/amdfam10: Use CAR_GLOBAL for sysinfoPatrick Georgi
This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24Remove duplicate VGA BIOS interrupt handlersPatrick Georgi
Some boards have two instances of the int15 handler that supports the onboard VGA BIOS, for YABEL and realmode. These are now similar enough that they can be deduplicated. Due to minor differences this requires manual effort. Change-Id: I03ae314cb90dd65d96591ce448504aa961cbeb88 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24yabel: Use X86_* instead of the more verbose M.x86.REG_*Patrick Georgi
Makes it more similar to what realmode looks like. Change-Id: I4407431f2d979c43dd186114d67ed11845907afe Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86 realmode: Use x86emu register file + definesPatrick Georgi
By using the (global) register file as defined by x86emu, we can use the same register access for YABEL and realmode interrupt handlers. - the x86 realmode interrupt handlers changed in signature - to access registers, use X86_$REGNAME now (eg. X86_EAX) - x86_exception_handler still uses struct eregs *regs to avoid spilling the x86emu register file stuff everywhere Coccinelle script that handled most of this commit: @ inthandler @ identifier FUNC, regs; @@ int FUNC( -struct eregs *regs +void ) { ... } @ depends on inthandler @ identifier regs; @@ -regs->eax +X86_EAX @ depends on inthandler @ identifier regs; @@ -regs->ebx +X86_EBX @ depends on inthandler @ identifier regs; @@ -regs->ecx +X86_ECX @ depends on inthandler @ identifier regs; @@ -regs->edx +X86_EDX @ depends on inthandler @ identifier regs; @@ -regs->esi +X86_ESI @ depends on inthandler @ identifier regs; @@ -regs->edi +X86_EDI @ depends on inthandler @ identifier regs; @@ -regs->eflags +X86_EFLAGS @ depends on inthandler @ identifier regs; @@ -regs->vector +M.x86.intno Change-Id: I60cc2c36646fe4b7f97457b1e297e3df086daa36 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86 realmode: Adapt to x86emu/YABEL style return codesPatrick Georgi
realmode int handlers must return the same codes as the YABEL int handlers now: 1 for "interrupt handled", 0 for "not handled" (ie. error). Change-Id: Idc01cf64e2c97150fc4643671a0bc4cca2ae6668 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Fix PIRQ routing abstractionStefan Reinauer
intel_irq_routing_table is a local structure that should not be used globally, because it might not be there on all mainboards. Instead, the API has to be corrected to allow passing a PIRQ table in where needed. Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop unneeded BOARD_HAS_FADT optionStefan Reinauer
Change-Id: Iaaeee87d70cf052bc7980007cdf1f7dda88b3623 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Reduce number of per-mainboard changesStefan Reinauer
- Add mainboard_smi.c from arch/x86/Makefile if it's there - Add mainboard's chromeos.c from the chromeos Makefile Change-Id: I3f80e2cb368f88d2a38036895a19f3576dd9553b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1835 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop CONFIG_HAVE_BUS_CONFIG, clean up KconfigStefan Reinauer
This patch is the beginning of a Kconfig cleanup series - drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it exists in the mainboard directory - drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig if it only defines the defaul value of 0 - Add mptable.c, fadt.c, reset.c and ssdtX.asl when they exist, not based on some Kconfig magic Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200 Reviewed-on: http://review.coreboot.org/1832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-14Move HAVE_SMI_HANDLER from mainboards to chipsetsStefan Reinauer
Change-Id: Ibb6606fe3996e377181872a4544600f2d58c5439 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1834 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09Get rid of hard coded strings in ACPI tablesStefan Reinauer
(cosmetical) Change-Id: I3e01d8fbf2d71abcfcbe47efedd2184566c91df7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1748 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-08hpet: common ACPI generationPatrick Georgi
HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-10-05Use mainboard_interrupt_handlers everywherePatrick Georgi
The previous commit provides a mainboard_interrupt_handlers implementation YABEL with identical semantics to the x86emu one, so let's use it in both cases. This eliminates the need for the int15_install() indirection, so let's drop that, too. Generated using the following coccinelle patch and manual cleanups (empty #if/#endif): @@ type T; identifier FUNCARR; expression INT, HANDLER; @@ -typedef T yabel_handleIntFunc; -extern yabel_handleIntFunc FUNCARR[256]; -FUNCARR[INT] = HANDLER; +mainboard_interrupt_handlers(INT, &HANDLER); @@ @@ -void int15_install(void) -{ -mainboard_interrupt_handlers(0x15, &int15_handler); -} @@ @@ -void int15_install(void) -{ -mainboard_interrupt_handlers(0x15, &int15_handler); ... mainboard_interrupt_handlers(0x15, &int15_handler); -} @@ @@ -int15_install(); +mainboard_interrupt_handlers(0x15, &int15_handler); Change-Id: I70fd780d7ebf1564a2ff7d7148411673f6de113c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1559 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1391 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-08-02AMD and GFXUMA: move setup_uma_memory() to northbridgeKyösti Mälkki
UMA region can be determined at any time after the amount of RAM is known and before the uma_resource() call. Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1379 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-26Drop mainboard chip.hStefan Reinauer
mainboard_config never worked right, at least not since we've had sconfig. Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that tried to use it anyways. Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1359 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26Remove copies of rtl8168.cPatrick Georgi
One copy was slightly different, but all the differences were commented out Change-Id: I3cc7b5621c681a1eb286f9b16ef3ebdce03abb6b Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1356 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-23AMD and GFXUMA: drop redundant use of lb_add_memory_range()Kyösti Mälkki
Use of uma_resource() in AMD northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: Ib5e49e851d6622d8ece9d6d612e245b3962b9167 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1233 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-07-16Move setup_uma_memory() to K8 northbridgeKyösti Mälkki
These boards had identical UMA code: amd/dbm690t amd/pistachio technexion/tim5690 technexion/tim8690 The ones below had whitespace or debug level change compared to the one above: kontron/kt690 siemens/sitemp_g1p1 These boards use AMDFAM10 guidelines in code: asrock/939a785gmh amd/mahogany Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1210 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Define global uma_memory variablesKyösti Mälkki
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 08:14:15 +0000