coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2016-02-18	southbridge/intel/bd82x6x: Use common gpio.c	Patrick Rudolph
2016-02-12	Merge sandy/ivybridge romstage flow for MRC and non-MRC.	Vladimir Serbinenko
2016-02-09	ivy: Add a possiblity for mainboard early init.	Vladimir Serbinenko
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-11-23	sandy/ivy/nehalem: Remerge interrupt handling	Vladimir Serbinenko
2014-10-24	sandy/ivy native: dedup romstage.c main()	Vladimir Serbinenko
2014-10-17	lenovo/t520: Use native raminit over MRC blob	Nicolas Reinecke
2014-10-16	bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.	Vladimir Serbinenko
2014-10-16	sandybridge: Move common northbridge finalize to northbridge code.	Vladimir Serbinenko
2014-08-25	lenovo/t520: fix PCIe interrupt and function disable config	Nicolas Reinecke
2014-08-24	lenovo/t520: replace dumped GPIO values with gpio.h	Nicolas Reinecke
2014-08-23	lenovo/t520: fix usb config & documentation	Nicolas Reinecke
2014-08-15	intel/cpu: rename car.h to romstage.h	Aaron Durbin
2014-08-14	Intel: Add common header file for CAR setup	Edward O'Callaghan
2014-06-20	sandy/ivy boards: Use acpi_s3_resume_allowed()	Kyösti Mälkki
2014-05-13	mainboard/lenovo: Add Lenovo Thinkpad T520 support	Zaolin