summaryrefslogtreecommitdiff
path: root/src/mainboard/ocp
AgeCommit message (Collapse)Author
2020-07-23mb/ocp/deltalake: Add ipmi POST start command in romstageTimChu
Add function to send POST start command to BMC. This function is used in romstage and the POST end command will be sent in u-root. TEST=Read POST command log in OpenBMC, if command received successfully, message may show as below, root@bmc-oob:~# cat /var/log/messages |grep -i "POST" 2020 Jul 15 16:36:11 bmc-oob. user.info fby3-v2020.23.1: ipmid: POST Start Event for Payload#2 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu@quantatw.com> Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/41605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23mb/ocp/deltalake: Implement SMBIOS type 9 -- system slots by SKUMorgan Jang
Create SMBIOS type 9 by getting PCIe config from BMC. TEST=Check SMBIOS type 9 is created correctly on different SKUs Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22mb/ocp/deltalake: Unset POWER_STATE_DEFAULT_ON_AFTER_FAILURETim Chu
Change PCH power policy. Set default of POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n in order to change power state to S5 when power is reapplied after power failure. TEST=Base on CB:42289, CB:43338 and build for Deltalake. The following Kconfig options must be selected: select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select CPU_INTEL_COMMON_SMM Boot the system and check the last bit of GEN_PMCON_B is set to 1 through ITP with command: pch.pm_dump Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I4d4f14bdfc18740976171fd5d369b2d79a916dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42976 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22mb/ocp/deltalake: Set FSP log level and add default values if VPD variables ↵Johnny Lin
are not found 1. Read VPD variable 'fsp_log_level' to decide FSP log level. 2. Define the default values when the VPD variables cannot be found, put all the values to vpd.h for better documentation and maintenance. Tested=On OCP DeltaLake, the fsp_log_level can be changed from the VPD variable. Change-Id: I44cd59ed0c942c31aaf95ed0c8ac78eb7d661123 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16Revert "mb/ocp/deltalake: Select IPMI OCP to send POST start/end command"Philipp Deppenwiese
This reverts commit a5ca4a0c75237093f1a4d90f30c0c932e5fcd05d. Reason for revert: Breaks coreboot tree because of non existent kconfig symbol Change-Id: Ib8f55dc2f6444690945bc2dc64baad5d0c39cdf4 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/ocp/deltalake: Select IPMI OCP to send POST start/end commandTimChu
Implement sending POST start/end command to BMC. TEST=Read POST command log in OpenBMC, if command received successfully, message may show as below, root@bmc-oob:~# cat /var/log/messages |grep -i "POST" 2020 May 28 13:21:22 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST Start Event for Payload#1 2020 May 28 13:21:25 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST End Event for Payload#1 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu@quantatw.com> Change-Id: I38b512ee97c0eda6ba54482a448ef9ffc27b4ddb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41993 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/ocp/deltalake: Config PCH PCIe ports in devicetreeMorgan Jang
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed are expected. Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-12mb/ocp/deltalake: Pull POST complete pin low before booting payloadJohnny Lin
Delta Lake uses GPIO pin GPP_B20 for POST complete event, BIOS needs to pull this pin low for BIC (Bridge IC) to start reading sensors. Tested=On Delta Lake oBMC, bic-util slotx --get_gpio to confirm the pin is low. Change-Id: I7e05f8a7caead8ee0632af4ff60ccd8b2412b3dd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-12mb/ocp/deltalake: Use VPD data to configure FSP UPD at romstageJohnny Lin
Read VPD variable 'fsp_log_enable' to decide enabling FSP log or not. With VPD_RW_THEN_RO, VPD_RW takes precedence over VPD_RO, and would be set to enabled if both places cannot find it. Tested=On OCP Delta Lake, use vpd to create and set fsp_log_enable and verified the results are expected. Change-Id: I0b3463acedd90e8e17f7e4eedc2fab63644f87e1 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: insomniac <insomniac@slackware.it>
2020-07-08mb/ocp/deltalake: Enable LPC IO 0x600 decode for BICBryant Ou
BIC uses LPCflash utility to flash FW, it uses LPC to send the bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support. TEST=Use LPCflash utility to flash BIC FW on YV3 successfully. [root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3). iBytesRead (0x00007c00). Discovering LPC boot loader. Discovered @ 0x3f8. Configuring LPC boot loader. Configured @ 0x00000600. Sending header block. Sent. Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete. Update done! Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/42856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in ↵Johnny Lin
romstage Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Tested on OCP Delta Lake. Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configsJohnny Lin
In romstage get the config from BMC IPMI and update the IIO accordingly. Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation register values are expected. Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-07vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt socJonathan Zhang
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also update memory map HOB definition file accordingly. The CPX-SP soc code is updated to direct FSP log to SOL. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Add VPD flash regions and select VPD and VPD_SMBIOS_VERSIONJohnny Lin
Tested on OCP Delta Lake. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMCJohnny Lin
There are 4 slots in YV3, Location In Chassis should be 1~4. Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct. Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMCJohnny Lin
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR for OEM string 1 to 6, add string 8 for PCIE configuration. 2. Set the read PPIN MSR to BMC. Tested on OCP Delta Lake. Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02mb/ocp: remove sonorapassJonathan Zhang
Sonora Pass server program was terminated. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I5354ea1e912fd25f0ac9851edf0461413ad8bb21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42948 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/ocp/deltalake: Enable IPMI KCSMorgan Jang
Config the IO port for IPMI KCS and set bmc_boot_timeout for checking BMC self test result. TEST=Check if the BMC IPMI reponse data is correct or not. Change-Id: I675060299b486986ebc39d8f714615b3e13de89a Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41023 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/ocp/deltalake: add RW_MRC_CACHE flash regionJonathan Zhang
Add RW_MRC_CACHE flash region to hold MRC cache data. With memory training skipped for subsequent reboots, the boot time is reduced by 8 minutes on OCP Delta Lake server, when FSP verbose logging is turned on. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I27ed00100e1ea9e29b0e71ea5a8397cd550e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42025 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/ocp/deltalake: Add OCP Delta Lake mainboardJonathan Zhang
OCP Delta Lake server is a one socket server platform powered by Intel Cooper Lake Scalable Processor. The Delta Lake server is a blade of OCP Yosemite V3 multi-host sled. TESTED=Successfully booted on both YV3 config A Delta Lake server and config C Delta Lake server. The coreboot payload is Linux kernel plus u-root as initramfs. Below are the logs of ssh'ing into a config C deltalake server: jonzhang@devvm2573:~$ ssh yv3-cth root@ip's password: Last login: Mon Apr 20 21:56:51 2020 from [root@dhcp-100-96-192-156 ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 52 On-line CPU(s) list: 0-51 ... [root@dhcp-100-96-192-156 ~]# cbmem 34 entries total: 0:1st timestamp 28,621,996 40:device configuration 178,835,602 (150,213,605) ... Total Time: 135,276,123,874,479,544 [root@dhcp-100-96-192-156 ~]# cat /proc/cmdline root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-07acpi: Rename motherboard_fill_fadt() to mainboard_fill_fadt()Kyösti Mälkki
The prefix mainboard_ was used everywhere else. Change-Id: Ie576fd47301aa484cb1396e0c6f7260b7698af4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-07mb/*: Remove some fadt.c filesKyösti Mälkki
Change-Id: I13ed3b6e8608c37c1ebe51838e4052f89a638d83 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41947 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-10src/mainboard: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I64d9468682a4aae3084b17b8724d035f17d01dff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01md/tiogapass: move all *.h to dir and make them globalMaxim Polyakov
It is necessary to rename the file gpio.h so that there are no conflict with another file (src/include/gpio.h) Change-Id: I4e3ef5882d6cb0ddbcb8357b54106ff2f47e4c51 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40733 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defsMaxim Polyakov
Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01mb/ocp/tiogapass: fix advanced _PAD_CFG_STRUCT macros in configMaxim Polyakov
If the current pad configuration can not be defined using standard macros from the gpio_defs.h [1], then the intelp2m utility generates "advanced" _PAD_CFG_STRUCT() macros. However, often this configuration in the vendor’s firmware is erroneous. Change the extended macros to standard ones taking into account the information based on the schematic diagram and the previous GPIO configuration for FSP-M [2]. [1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h Change-Id: I56e45b1df77acbdd67e6325c3745a7ad137f8805 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-05-01mb/ocp/tiogapass: rework GPIOs configuration using macrosMaxim Polyakov
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input (GPI). The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40731 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/tiogapass: use common driver to configure GPIOMaxim Polyakov
According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with AMI firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file tiogapass/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39427 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/ocp/sonorapass: Populate FSP-M parametersAndrey Petrov
Since CPX FSP headers are not released yet, populate certain settings with hard-coded offsets. Provided values are probably not correct and I do not understand what they mean and there is no documentation available yet. However they were found to work to a certain degree. TEST=tested on OCP Sonora Pass EVT Change-Id: I0f78cde69cb8a49a388a412b97bf8713e5b380ea Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40554 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/ocp/sonorapass: Add Sonora PassRyback Hung
Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com> Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-05-01mb/ocp/tiogapass: Update UPD IIO bifurcation at run-timeJohnny Lin
Update UPD IIO bifurcation at run-time according to different Riser cards. For detail please reference Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types. With the engineering build FSP, it can only configure IIO for one socket so my local test needs to remove all socket1 elements from tp_iio_bifur_table. This change relies on [1] and need to add GPP_C15 and GPP_C16 to early_gpio_table for gpio configuration in bootblock. [1] https://review.coreboot.org/c/coreboot/+/39427/ Tested=OCP Tioga Pass can see socket0 IIO being updated with an engineering build FSP. Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-30mb/ocp/tiogapass: Implement port 80h direct to GPIO and init UART pinsBryantOu
Enable aspeed's function that port 80h direct to GPIO for LED display, refer to section 9.4 Port 80h Direct to GPIO Guide of aspeed's Application Design Guide, also configure GPIO to UART for output serial console messages. Tested=Check if port 80h LED debug card can display POST codes at early stage, and serial console can see the related messages. Change-Id: I087d5a81b881533b4550c193e4e9720a134fb8e7 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40481 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18mb/ocp/tiogapass: Pull POST complete pinBryantOu
Tioga Pass platform use GPIO pin of GPP_B20 for POST complete, BIOS needs to configure this pin for BMC to poll, so it knows when to start to access other components. Tested=Read GPIO status (GPIOAA7) in OpenBMC, the value is 0, the command and result are shown as below, root@bmc-oob:~# cat /tmp/gpionames/FM_BIOS_POST_CMPLT_N/value 0 root@bmc-oob:~# Change-Id: I134f80153461c5acd872587038a2207586b658dd Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-04-14mb/ocp/tiogapass: Add missing spaces around operatorsPaul Menzel
Change-Id: I8930e96e5f2c45b8658dc4dfe1ab57d573e7b26f Fixes: b75bcc978a ("mb/ocp/tiogapass: Properly configure early serial output") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-06mainboard/ocp: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I136e19fbba22b71676a0163a88ae341356c31271 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40088 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-26mb/ocp/tiogapass: Properly configure early serial outputAndrey Petrov
Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However we currently do not configure/enable SuperIO chip. As a result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible. This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible. TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock. Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-03-26soc/intel/xeon_sp: Refactor code to allow for additional CPUs typesAndrey Petrov
Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25mb/ocp/tiogapass: Enable IPMI KCSJohnny Lin
A bigger than zero value of bmc_boot_timeout must be set for KCS ipmi_get_bmc_self_test_result() to run, otherwise the self test result will be error and won't write SMBIOS type 38 table. Here we set 60 seconds as the maximal self test timeout. Tested=Check if the BMC IPMI response data and SMBIOS type 38 on OCP Tioga Pass are correct or not. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-18mainboard/[g-p]*: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I426518e8e18de1c8efcfb7ecb0835df3e257dca1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39608 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binariesNico Huber
If we don't pretend to have binaries, there is no need to add fake ones. This also fixes building the default config. Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mainboard/ocp: Add support for OCP platform TiogaPassJonathan Zhang
OCP platform Tiogapass is a 2-socket server platform, which is based on a chipset including Intel Skylake-SP processors and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon Scalable Processor family. Following ACPI tables are added: DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR This patchset is tested on a Tiogapass board. It booted with Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets, 18 cores, 2 thread per core); ssh command shows networking is up from Mellanox ConnectX-4 PCIe NIC card. Towards successful gerrit buildbot build, note that: * microcode is in coreboot intel-microcode submodule repo. * IFD binary is included in this patch. * Dummy ME binary is used, as it may take long time for Intel ME binary to be available in public domain. * Fake FSP binary is used, as at this moment the SKX-SP FSP binary is not going to be available in public domain. Known issues (Not intend to address in this initial support for Xeon-SP processors): * c6 state is not supported. * dsdt table is not fully populated, such as processor/socket devices, some PCIe devices. * SMM handlers are not added. Following are some command execution with CentOS booted from local SATA disk: [root@localhost ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 72 On-line CPU(s) list: 0-71 Thread(s) per core: 2 Core(s) per socket: 18 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz Stepping: 4 CPU MHz: 140.415 BogoMIPS: 4626.46 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 25344K NUMA node0 CPU(s): 0-17,36-53 NUMA node1 CPU(s): 18-35,54-71 [root@localhost ~]# ifconfig eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 inet 172.23.68.190 netmask 255.255.0.0 broadcast 172.23.255.255 inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0 prefixlen 64 //cut inet6 fe80::268a:7ff:fe57:5af0 prefixlen 64 scopeid 0x20<link> inet6 2620:10d:c082:9063::5d2 prefixlen 128 scopeid 0x0<global> ether 24:8a:07:57:5a:f0 txqueuelen 1000 (Ethernet) RX packets 84249 bytes 6371591 (6.0 MiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 8418 bytes 748781 (731.2 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536 inet 127.0.0.1 netmask 255.0.0.0 inet6 ::1 prefixlen 128 scopeid 0x10<host> loop txqueuelen 1000 (Local Loopback) RX packets 613 bytes 63906 (62.4 KiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 613 bytes 63906 (62.4 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 [root@localhost ~]# cbmem 36 entries total: // Lines were cut to avoid checkpatch.pl warnings Total Time: 96,243,882,140,175,829 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-21mb/*/*: Remove BROADWELL_DE boardsArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-10-24mb/ocp/monolake: Configure IPMI BMC FRB2 watchdog timer via VPD variablesJohnny Lin
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Right now the timer is started after FSP-M. Ideally it should be before FSP-M (to detect memory training error). Tested on OCP Mono Lake. Change-Id: I82b244d08380a0461c92662e025d8b95b3133e23 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-06mb/ocp/monolake: Add GPIO table to initialize custom configsJingle Hsu
Add a GPIO table for Monolake to initialize GPIOs with custom board configurations. Tested on Monolake. Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 05:13:05 +0000