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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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path:
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src
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mainboard
/
pcengines
/
apu1
/
devicetree.cb
Age
Commit message (
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Author
2020-03-25
mb/pcengines/*/devicetree: remove non-existing NCT5104d LDN 0xe
Michał Żygowski
2020-03-18
mainboard/[g-p]*: Remove copyright notices
Patrick Georgi
2020-01-20
mb/pcengines/*: enable simple IO-based GPIO control
Piotr Kleinschmidt
2020-01-15
mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft reset
Piotr Kleinschmidt
2019-01-16
src/mainboard/pcengines/apu1: Enable LPC TPM
Michał Żygowski
2019-01-16
AGESA fam14 boards: Clean up devicetree
Kyösti Mälkki
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-29
pcengines/apu1: adapt comments in devicetree to board
Felix Held
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-05-19
pcengines/apu1: Add switch between UART and GPIO modes
Kyösti Mälkki
2015-02-23
pcengines/apu1: Fix 0:15.x PCIe root ports
Kyösti Mälkki
2015-02-23
pcengines/apu1: Fix and clean up devicetree
Kyösti Mälkki
2015-02-23
pcengines/apu1: Implement board GPIOs
Kyösti Mälkki
2015-02-23
pcengines/apu1: New board PC Engines APU1
Kyösti Mälkki
2015-02-23
pcengines/apu1: Fork of amd/persimmon
Kyösti Mälkki