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coreboot
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autoport-hsw
broadwell_refcode
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Some coreboot project code with my work
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path:
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mainboard
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pcengines
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apu2
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romstage.c
Age
Commit message (
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Author
2018-11-08
src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2
Michał Żygowski
2018-08-04
mb/pcengines/apu2: change GPIO setting
Michał Żygowski
2018-07-25
drivers/tpm: Add TPM ramstage driver for devices without vboot.
Philipp Deppenwiese
2018-07-02
src: Get rid of unneeded whitespace
Elyes HAOUAS
2018-06-04
security/tpm: Unify the coreboot TPM software stack
Philipp Deppenwiese
2018-01-18
security/tpm: Change TPM naming for different layers.
Philipp Deppenwiese
2018-01-18
security/tpm: Move tpm TSS and TSPI layer to security section
Philipp Deppenwiese
2017-12-21
pcengines/apu2: add support for apu4 variant
Piotr Król
2017-10-20
mainboard/pcengines/apu2: add apu3 and apu5 variants
Kamil Wcislo
2017-10-19
pcengines/apu2: Add timestamps to romstage
Michał Żygowski
2017-07-17
binaryPI: Disable CAR with empty stack
Kyösti Mälkki
2017-05-11
mainboard/pcengines/apu2: Add LPC TPM support
Philipp Deppenwiese
2017-03-08
binaryPI boards: Drop any ACPI S3 support
Kyösti Mälkki
2016-12-19
pcengines/apu2: add board support
Piotr Król