coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-07-29	soc/intel/skylake: Enable TraceHub depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable SMBus depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable LAN depending on devicetree configuration	Felix Singer
2020-07-29	soc/intel/skylake: Enable SATA depending on devicetree configuration	Felix Singer
2020-07-26	skylake boards: Factor out copy-pasted PIRQ routes	Angel Pons
2020-06-21	mb/protectli/vault_kbl: Enable Intel PTT	Michał Żygowski
2020-06-02	src: Remove unused 'include <bootstate.h>'	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-04	soc/intel/skl: always enable SataPwrOptEnable	Michael Niewöhner
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
2020-04-05	fsp2_0: Clean up around `config FSP_USE_REPO`	Nico Huber
2020-03-10	mb/protectli/vault_kbl: Add FW6 support	Michał Żygowski