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2017-01-06sb/ich7: Use common/gpio.h to set up GPIOsArthur Heymans
This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-04intel/i945 boards: Add romstage time stampsPaul Menzel
Currently, some Intel 945 boards miss some or all of the time stamps *1:start of rom stage*, *2:before ram initialization*, and *3:after ram initialization*, so add them. Use the same formatting as used for the board Lenovo X60, which already has code for all the time stamps. Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-15mb/roda/rv11: Add new boards Lizard RV11 and RW11Dennis Wassenberg
The Roda Lizard RV11 is a comparatively lightweight, full-rugged notebook. It's based on a 17W TDP dual core Ivy Bridge CPU. The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o options). The RV11 is the first board to use the native graphics initialization by libgfxinit. Tested so far, are the internal eDP port, DP and VGA. Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-11nb/intel/i945: Make pci_mmio_size a devicetree parameterArthur Heymans
Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. A safe minimum of 768M is also defined since using anything less causes problems (if 4G of ram is used). Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16856 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-11intel/gm45: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setupKyösti Mälkki
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With this change, CBMEM region is set early-on as WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10mainboard/roda/rk9: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/roda/rk9. Change-Id: I56fec2a2814ee4b91b11f71dbdca1271792cd0e5 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17302 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10mainboard/roda/rk886ex: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/roda/rk886ex. Change-Id: I2e88adc444dbbde7a4344829d7bd5a6c9e1f7531 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17301 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/roda: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I4ce2705a8a07d0388bbdb459b63b59fc10a3aa39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16929 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04nb/gm45: allow use of 352M preallocated ram for igdArthur Heymans
The datasheets on gm45: "Mobile Intel® 4 Series Express Chipset Family" mention the possibility of having 352M ram preallocated for the integrated graphic device. This only worked fine if the amount of ram in the system was 3GB or less. When 4G or more is installed, memory is remapped to create a 1GB large pci mmio hole which is not enough and creates conflicts when 352M vram is used. This patch increases the pci mmio hole size on Lenovo x200 to allow 352M vram to work. TEST: build and flash on target with 4GB ram or more, use nvramtool to set gfx_uma_size to 352M and reboot. Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16831 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-26mainboard/*/*/mptable.c: Improve code formattingElyes HAOUAS
Change-Id: I341293cd334d6d465636db7e81400230d61bc693 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/lenovo-winent: Add space around operatorsElyes HAOUAS
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-31i945: Enable changing VRAM sizeArthur Heymans
On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states. What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge. TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-26intel/gm45: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I3148dbbcb06676f48b6bc357124403b70b9bcb6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15246 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-21intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12nb/intel/raminit (native): Read PCI mmio size from devicetreePatrick Rudolph
Instead of hardcoding the PCI mmio size read it from devicetree. Set a default value of 2048 MiB and 1024MiB for laptops without discrete graphics. Tested on Sandybridge Lenovo T520. Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-04gm45: enable setting all vram sizes from cmosArthur Heymans
Setting the size of the preallocated memory for the igd is done using a cmos parameter, gfx_uma_size. This was limited to a subset of all available sizes, that were already implemented elsewhere in the northbridge code. What this does is change the cmos parameter to 4 bits instead of 3 bits to accomodate all vram sizes. It also adds a sane default of 32mb that already was in place. The northbridge code that reads this cmos parameter is also changed for this new cmos settings. 352M is disabled since it causes issues on systems with 4GB or more ram. TEST: Build, flash target. Clear cmos by corrupting the checksum (nvramtool -c something). Set a desired value in gfx_uma_size using nvramtool. "dmesg | grep stolen" to see what is actually allocated. Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14900 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-03-08roda/rk9: Remove #include early_serial.c from romstageAntonello Dettori
Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Also re-organize some of the superio code in order to succesfully compile the rom. Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/13925 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09rx886ex: Fix PBIF reference.Vladimir Serbinenko
PBIF is package and so a scalar can't be stored instead of it. What was meant is probably Index(PBIF, 0) Change-Id: Iddd18e1f165e0f48fd91124200aba5c6b4a5b4bd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13621 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01drivers/pc80: Add PS/2 mouse presence detectTimothy Pearson
On certain Winbond SuperIO devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. Add auxiliary channel PS/2 device presence detect, and update the Winbond W83667HG-A driver to flag the auxiliary channel as disabled if no device was detected. Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-13[WIP] mb/roda/rk9: Enable CONFIG_HAVE_ACPI_RESUMENico Huber
Change-Id: Ifa7dd593f70921a99d937104960e26100de28089 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12421 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-18mb/roda/rk9: Fix cbmem recovery on resume pathNico Huber
By calling cbmem_recovery() with `0`, we rewrote the cbmem table even on the resume path. By that, we lost the OS' resume vector and ended up loading the payload. Change-Id: Ic24a12d4143d6924321b1d01f07a467c58c4e9ea Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/12420 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-05intel/i945: Consolidate MADT handlingVladimir Serbinenko
Change-Id: Ic3cdfa6086a45aa231aa817d5ef6998823589818 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7108 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-23roda/rk9: Consolidate `acpi/platform.asl`Paul Menzel
The ASL code is already present in `southbridge/intel/common/acpi/platform.asl` and `cpu/intel/common/acpi/cpu.asl`. So include these files instead of duplicating the code. Something similar was don in commit commit 24813c14 (i945: Consolidate acpi/platform.asl). Change-Id: Ifb434db1b8eb01acf48f26366c5237ae49a8730a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23southbridge/intel: Move `i82801gx/acpi/platform.asl` to `common/acpi`Paul Menzel
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact same ASL code though. So share this in the directory `src/southbridge/intel/common/acpi`. Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/cpu/intel/model_6dx/acpi`, although the devices can also use different Intel CPU models like, for example, `intel/model_6ex` on the Lenovo T60. Therefore move the file to the directory `src/cpu/intel/common/acpi` so that other devices, like Intel GM45 based devices, can also include it. Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22gma ACPI: Make brightness levels a per board settingNico Huber
Those are actually board specific. Keep the old value as defaults, though. The defaults are included by all affected boards. Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11705 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-28igd.asl rewriteVladimir Serbinenko
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-26speedstep: Don't supply weak get_cst_entries.Vladimir Serbinenko
This should be overriden by mobo even if it's no-op override. weak function in this case would only hide real problems. Change-Id: I30dd671eb605b490a51153d00ae308c4bdef3d05 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26gm45: Link cstates.c rather than including it.Vladimir Serbinenko
The comment about necessity of include isn't true anymore as get_cst_entries is not weak anymore so if it's not found, the linking would fail. Change-Id: I4bf88208d63ac3e625f464c3907e2e1ea575dd9f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7375 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-20acpi: make fill_slit and fill_srat into arguments.Vladimir Serbinenko
SLIT and SRAT are created this way only on amdk8 and amdfam10. This saves the need of having a lot of dummies. Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7052 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19Move smi trap sample to documentation, don't keep it in every mobo.Vladimir Serbinenko
Sample code belongs to documentation, not copied 100x over prodcution code. Change-Id: I6bb318d76057d02bd6ac5641d12d56ab6d60b745 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10229 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-02-16acpi: Generate valid ACPI processor objectsTimothy Pearson
The existing code generated invalid ACPI processor objects if the core number was greater than 9. The first invalid object instance was autocorrected by Linux, but subsequent instances conflicted with each other, leading to a failure to boot if more than 10 CPU cores were installed. The modified code will function with up to 99 cores. Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8422 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16mainboard/cmos: Delete obsolete commented parametersTimothy Pearson
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8459 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-06mainboard/*/romstage.c: Sanitize system header inclusionsEdward O'Callaghan
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06Remove IRQ_SLOT_COUNT on all boards without PIRQ table.Vladimir Serbinenko
This config is used only to generate PIRQ table. If no such table is supplied there is no need for config. Change-Id: I537d440f53019a6bf7f190446074e75e7420545a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7566 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-03i945: Consolidate acpi/platform.aslVladimir Serbinenko
Change-Id: Iccb2dda8a427e483c04693e46b00e0bc2452a26b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7086 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-03i82801gx: Enable upper CMOS in bootblock.Vladimir Serbinenko
Otherwise checksum may not work correctly on early stages. For compatibility with old bootblocks also enable it early in romstage. Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-14mainboard: Remove commented include lines for mc146818rtc.hEdward O'Callaghan
Change-Id: I4d830d988b74f2403ef8979cbafcaee3018fea62 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7423 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-09i945: consolidate sb & nb early initsVladimir Serbinenko
Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7062 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-09i945: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Idc3522807b17e56bdaf8f04b4bd68c6ed9777363 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7110 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
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