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DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ic08b191ee4dbcc56eb482601aa268394545936ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29292
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I80dd65484fd52e9048635091fb20a123e959e999
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27869
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.
Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.
Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.
Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.
Test: boot various google/samsung boards, verify SSDT created with
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux
Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for libgfxinit
Test: boot stumpy, verify all outputs operational prior for pre-OS display
Change-Id: Ia720814c2225502316de5c5e9639c67df65a2ed0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ife344d1699a2eff7d93738221a0e87d0481f05d7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.
* Add TPM driver in ramstage chip init which calls the tpm_setup
function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
in ramstage.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also remove some unnedded includes.
Change-Id: I036208a111d009620d8354fa9c97688eb4e872ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I4f82482595b0e6c6159c6e1c66158bc18b061f04
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In the end it does not look like RCBA register offsets are fully
compatible over southbridges.
This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.
Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.
Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t has been abandoned in ramstage.
Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage.
Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26984
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t has been abandoned in ramstage.
Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I0aefe25e3af61c747c06629e365b8e27459181aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Currently the throttle event handler method THRM is defined as an
extern on the intel bd82x6x and lynxpoint chipsets, then defined
again in the platform with thermal event handling. In newer versions
of IASL, this generates an error, as the method is defined in two
places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
This also requires moving the thermal handler, which now includes
the define to before the gnvs asl file.
TEST=Build before and after, make sure correct code is included.
Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26123
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use SUPERIO_DEV for global control device instead of DUMMY_DEV.
Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25852
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a
common location) makes some platforms use the wrong OIC register defi-
nition. It was extended to 16-bit in the corporate version of ICH10.
So let's give the new size and location a new name: EOIC (extended OIC).
This only touches the systems affected by the mentioned change. Other
platforms still need to be adapted before they can use the common RCBA
definitions.
Change-Id: If9e554c072f01412164dc35e0b09272142e3796f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/24924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Many generations of Intel hardware have identical code concerning the
RCBA.
Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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* Rename tlcl* to tss* as tpm software stack layer.
* Fix inconsistent naming.
Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
(sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X.
This generates the main ACPI _PRT table automatically based on the
chipset registers.
Tested on Intel NUC DCP847SKE with Linux 4.13.14:
$ cat /proc/interrupts
CPU0 CPU1
0: 23 0 IO-APIC 2-edge timer
8: 1 0 IO-APIC 8-edge rtc0
9: 0 0 IO-APIC 9-fasteoi acpi
19: 86 0 IO-APIC 19-fasteoi ehci_hcd:usb1
23: 0 0 IO-APIC 23-fasteoi i801_smbus
[...MSI and other interrupts skipped...]
Log messages:
ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6
ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4
ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4
ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8
ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1
Generated _PRT:
Scope (\_SB.PCI0)
{
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
0x00000000,
0x00000015
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
0x00000000,
0x00000017
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
0x00000000,
0x00000010
}
})
}
Else
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKF,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKH,
0x00000000
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
}
})
}
}
}
Change-Id: I832a86925283d61b64b8268246d9e6f11994c120
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
Change-Id: Id98aa5f6dbdcbb8da4616d4fce6e7388f3ba4656
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With the existing SSID, the driver loaded by Windows results
in the headphone jack and internal mic being non-functional.
With the new SSID, the a functional driver is loaded and
everything works correctly. Linux works correctly with
either SSID so the change has no impact there.
New SSID extracted from Windows drivers (.inf).
Change-Id: I4195d00d6b18dcd0039747d9883cdf8e1a76f461
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Fix comments to reflect correct manufacturer/model, SSID.
Change-Id: Ibaa39fbb8081393ef4696c6f2470a546e801f483
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch attempts to finish the separation between CONFIG_VBOOT and
CONFIG_CHROMEOS by moving the remaining options and code (including
image generation code for things like FWID and GBB flags, which are
intrinsic to vboot itself) from src/vendorcode/google/chromeos to
src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig
options, and clean up menuconfig visibility for them (i.e. some options
were visible even though they were tied to the hardware while others
were invisible even though it might make sense to change them).
CQ-DEPEND=CL:459088
Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18984
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The virtualized developer switch was invented five years ago and has
been used on every vboot system ever since. We shouldn't need to specify
it again and again for every new board. This patch flips the Kconfig
logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with
CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to
set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the
latter for Lumpy which seems to have been omitted incorrectly, and hide
it from menuconfig since it's a hardware parameter that shouldn't be
configurable.)
Since almost all our developer switches are virtual, it doesn't make
sense for every board to pass a non-existent or non-functional developer
mode switch in the coreboot tables, so let's get rid of that. It's also
dangerously confusing for many boards to define a get_developer_mode()
function that reads an actual pin (often from a debug header) which will
not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set.
Therefore, this patch removes all those non-functional instances of that
function. In the future, either the board has a physical dev switch and
must define it, or it doesn't and must not.
In a similar sense (and since I'm touching so many board configs
anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC.
Instead, it should just be assumed by default whenever a Chrome EC is
present in the system. This way, it can also still be overridden by
menuconfig.
CQ-DEPEND=CL:459701
Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18980
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Replace the use of the old device_t definition inside
mainboard/samsung/stumpy.
Change-Id: Ie6209b3b40d9aad0723690e7aeb3edfd0bfcc4a8
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17304
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Replace the use of the old device_t definition inside
mainboard/samsung/lumpy.
Change-Id: I39fe6bad42b3b0772d09d0fa7af357b797b8e04f
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17303
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17735
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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When MRC cache is available, first read only the SPD unique
identifier bytes required to detect possible DIMM replacement.
As this is 11 vs 256 bytes with slow SMBus operations, we save
about 70ms for every installed DIMM on normal boot path.
In the DIMM replacement case this adds some 10ms per installed DIMM
as some SPD gets read twice, but we are on slow RAM training boot path
anyways.
Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17491
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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commit 80EF7B7 [IT8772F: Clean up it8772f includes and add a LED API]
broke power LED operation when it incorrectly transferred
values from the old function (it8772f_gpio_setup) to the new one (
it8772f_gpio_led). Restore the correct values so power LED illuminates
when powered on.
Change-Id: I99a38351bb52063fafa7436e6397a8da7fc1e952
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17266
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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On-board memory is on channel 1.
This fixes native raminit with 4GiB SO-DIMM installed.
Change-Id: If1b94e050d7e8d0dbd349c0415a182730aa5fa90
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/16845
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I1ffee53a04df6874f658feb3d6ce7d5c7b922837
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16818
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.
To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).
Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package. Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.
Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.
BUG=chrome-os-partner:55639
Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The mainboard_smi_sleep() function takes ACPI sleep values
of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure
that whatever hardware PM1 control register values are used
the interface to the mainboard is the same. Move all the
SMI handlers in the mainboard directory to not open code
the literal values 3 and 5 for ACPI_S3 and ACPI_S5.
There were a few notable exceptions where the code was
attempting to use the hardware values and not the common
translated values. The few users of SLEEP_STATE_X were
updated to align with ACPI_SX as those defines are
already equal. The removal of SLEEP_STATE_X defines is
forthcoming in a subsequent patch.
BUG=chrome-os-partner:54977
Change-Id: I76592c9107778cce5995e5af764760453f54dc50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15664
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Broken with commit:
2585209 mb/samsung/lumpy/romstage: read SPD data of removable DIMM
The blob can pick SPDs from the addresses defined in pei_data
and we do only define read_spd() with USE_NATIVE_RAMINIT.
Change-Id: Ibd6d7a4a53fa808b476d3060872cb10d3dfce534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15329
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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