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path: root/src/mainboard/siemens/mc_apl1/variants/mc_apl3
AgeCommit message (Expand)Author
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-04mainboard/siemens: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-18mainboard/[^a-p]*: Remove copyright noticesPatrick Georgi
2019-10-18mb/siemens/mc_apl{3,5}: Remove __weak symbol from GPIO functionsWerner Zeh
2019-07-12mb/siemens/mc_apl3: Enable LPSS UART 1Mario Scheithauer
2019-07-11mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168Mario Scheithauer
2019-07-11mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed modeMario Scheithauer
2019-05-29src/mainboard: Add missing 'include <types.h>'Elyes HAOUAS
2019-04-15mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variantsWerner Zeh
2019-03-04arch/io.h: Add missing includesKyösti Mälkki
2018-11-16mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VARElyes HAOUAS
2018-11-16mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov
2018-11-12siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer
2018-11-12siemens/mc_apl3: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
2018-11-12siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer
2018-11-12siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer
2018-11-12siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
2018-11-07siemens/mc_apl3: Disable I2C7 over devicetreeMario Scheithauer
2018-11-07siemens/mc_apl3: Enable all PCIe root portsMario Scheithauer
2018-11-07siemens/mc_apl3: Remove reduced clock rate for I2C0Mario Scheithauer
2018-11-07siemens/mc_apl3: Disable CLKREQ of PCIe root portsMario Scheithauer
2018-11-07siemens/mc_apl3: Adjust GPIO settings for mc_apl3Mario Scheithauer
2018-10-30siemens/mc_apl3: Add new mainboard variant mc_apl3Mario Scheithauer
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