| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-05-29 | src/mainboard: Add missing 'include <types.h>' | Elyes HAOUAS |
| 2018-11-29 | siemens/mc_apl5: Disable PCI clock outputs on XIO bridges | Mario Scheithauer |
| 2018-11-29 | siemens/mc_apl5: Set bus master bit for on-board PCI device | Mario Scheithauer |
| 2018-11-18 | siemens/mc_apl5: Add new mainboard variant mc_apl5 | Mario Scheithauer |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |