| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-11-11 | mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge | Werner Zeh |
| 2019-11-11 | mb/siemens/mc_apl6: Add new mainboard based on mc_apl3 | Werner Zeh |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |