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broadwell_refcode
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Some coreboot project code with my work
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siemens
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mc_apl1
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variants
Age
Commit message (
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Author
2019-06-21
siemens/mc_apl5: Change PTN interface settings
Mario Scheithauer
2019-06-21
siemens/mc_apl5: Enable TPM support
Mario Scheithauer
2019-06-06
siemens/mc_apl5: Add own GPIO table
Mario Scheithauer
2019-05-29
src/mainboard: Add missing 'include <types.h>'
Elyes HAOUAS
2019-05-06
mb/siemens/mc_apl2: Limit SD-Card speed to DDR50
Werner Zeh
2019-04-15
mb/siemens/mc_apl4: Remove usage of external RTC
Werner Zeh
2019-04-15
mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants
Werner Zeh
2019-04-08
siemens/mc_apl5: Remove reduced clock rate for I2C0
Mario Scheithauer
2019-04-04
siemens/mc_apl4: Provide CLK on APL Pin PMU_SUSCLK
Uwe Poeche
2019-03-15
mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>'
Elyes HAOUAS
2019-03-06
mb/siemens/{mc_apl1,mc_tcu3}: Fix typo on "Display"
Elyes HAOUAS
2019-03-04
arch/io.h: Add missing includes
Kyösti Mälkki
2019-02-13
siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4
Uwe Poeche
2019-02-13
siemens/mc_apl2: Remove double entry from devicetree
Mario Scheithauer
2019-02-05
mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5
Werner Zeh
2019-01-30
siemens/mc_apl2: Change SERIRQ mode
Mario Scheithauer
2019-01-30
siemens/mc_apl2: Correct whitespace of devicetree
Mario Scheithauer
2019-01-30
siemens/mc_apl2: Activate TPM support
Mario Scheithauer
2019-01-16
siemens/mc_apl4: Change UART_FOR_CONSOLE index
Mario Scheithauer
2018-12-17
siemens/mc_apl4: Enable RTC RX6110SA on this mainboard
Uwe Poeche
2018-12-17
siemens/mc_apl4: Enable LVDS Display on mc_apl4
Uwe Poeche
2018-12-17
siemens/mc_apl4: Add GPIO configuration
Uwe Poeche
2018-11-29
siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-29
siemens/mc_apl5: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-29
siemens/mc_apl5: Enable SDCARD
Mario Scheithauer
2018-11-27
siemens/mc_apl5: Adjust the settings for the PCIe root ports
Mario Scheithauer
2018-11-26
siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read
Mario Scheithauer
2018-11-23
siemens/mc_apl4: Set CPU clock to minimum ratio
Werner Zeh
2018-11-18
siemens/mc_apl5: Add new mainboard variant mc_apl5
Mario Scheithauer
2018-11-16
mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VAR
Elyes HAOUAS
2018-11-16
src: Remove unneeded include <lib.h>
Elyes HAOUAS
2018-11-16
mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree
Peter Lemenkov
2018-11-16
siemens/mc_apl4: Clean up ramstage
Mario Scheithauer
2018-11-16
siemens/mc_apl4: Overwrite swizzle data for LPDDR4
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Enable SDCARD
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove external RTC from I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Enable all PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Remove the correction of the Tx signal for SATA
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
Mario Scheithauer
2018-11-07
siemens/mc_apl4: Add new mainboard variant mc_apl4
Mario Scheithauer
2018-11-07
siemens/mc_apl2: Adjust GPIO settings for mc_apl2
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable I2C7 over devicetree
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Enable all PCIe root ports
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable CLKREQ of PCIe root ports
Mario Scheithauer
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