Age | Commit message (Collapse) | Author |
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Use the 96 character limit for pad macros.
Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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GPIO Driver mode is used for configuration interrupt routing for
external devices through GPI. But there is no point in configuring
this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro
with others that do not set the corresponding bit in the Host Software
Pad Ownership register.
Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I7b656f0244774cb174a90d97c5ae1c725802b636
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Currently, those who want to use measured boot implemented within
vboot should enable verified boot first, along with sections such
as GBB and RW slots defined with manually written fmd files, even
if they do not actually want to verify anything.
As discussed in CB:34977, measured boot should be decoupled from
verified boot and make them two fully independent options. Crypto
routines necessary for measurement could be reused, and TPM and CRTM
init should be done somewhere other than vboot_logic_executed() if
verified boot is not enabled.
In this revision, only TCPA log is initialized during bootblock.
Before TPM gets set up, digests are not measured into tpm immediately,
but cached in TCPA log, and measured into determined PCRs right after
TPM is up.
This change allows those who do not want to use the verified boot
scheme implemented by vboot as well as its requirement of a more
complex partition scheme designed for chromeos to make use of the
measured boot functionality implemented within vboot library to
measure the boot process.
TODO: Measure MRC Cache somewhere, as MRC Cache has never resided in
CBFS any more, so it cannot be covered by tspi_measure_cbfs_hook().
Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I18e513cefc373b1cd70d31d1159928cc948a8476
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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This patch replaces and cleans up the redundant PTN3460 driver files in
/mainboard/siemens directories by using the now available driver in
src/drivers/i2c/ptn3460 and providing mainboard specific functions to
the driver.
TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...).
Change-Id: I976a502e7176a356bab772758250db3cdff529b9
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36643
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This mainboard needs VT-d to be enabled. Do so in devicetree.
Change-Id: I9f2f733163be019ac329660d7633b48c5d7896f1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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The TPM chip needs to be added to the devicetree so that the ACPI tables
will be generated for it. These ACPI table entry is used by the OS to get
the location of the TPM chip.
Change-Id: Ic40d1cf236dd849f04f088808d94b6dd81e3238a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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This mainboard variant uses SD-card and not eMMC. Therefore eMMC
controller is disabled while SDHCI is enabled.
Change-Id: I40b314905730b5d74c674d2251f8a4e5c807805f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36676
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On this mainboard variant the PCIe-2-PCI bridge is used a bit different.
Adjust the switched off clock lines to match the mainboard
configuration.
Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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mc_apl6 uses VBOOT scheme so enable it as default.
Change-Id: I341180f3815ff9f3b2db801d9d989119a2585b03
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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This patch adds a new mainboard variant called mc_apl6 which is based
on mc_apl3. So far only the names have been adjusted with no further
changes. Following commits will introduce the needed changes for this
mainboard variant.
Change-Id: Ic935f6cc1f037947b2c167696d40da8309e4d4f0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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The two GPIO functions variant_gpio_table() and
variant_early_gpio_table() provide the pointer to the variants GPIO
table for late and early GPIO init. As these functions are variant
dependent the keyword __weak must not be used as otherwise the linker
might choose the tables from the baseboard.
This patch removes the __weak definition making these functions
overriding the general ones in baseboard/gpio.c.
Change-Id: Ic7fc816d40cb112d7ab51089c3962a77798c08a8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36094
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.
Change-Id: I3d58094256d2730dbd249291a8f1ed8df9dfe62d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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To avoid possible panel failures due to incorrect timing settings for
PTN3460, the internal graphic device should be disabled.
Change-Id: Ie0b9ed99fb78461bb48d6f2ff328643cd8c2cd15
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Correct all GPIOs with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
In additional, set an internal pull to any GPI that does not have an
external resistor so that the input is not in an undefined state.
Change-Id: Ia8fe457eddbed0f4ee6bff9ef9dd7a92545be40b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
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The limitation for SD-Card was originally only made for mc_apl2
mainboard. Since other mc_apl mainboards also use the SD-Card interface,
the speed mode setting is made in the parent mainboard_final.
In additional, all UHS-I bus speed modes are disabled because of a
limitation for industry use cases. This means that only HS mode is
permitted.
Change-Id: I2f1b51f13a53c2507c52d6a169d6384b8570b3bc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is
activated.
Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This GPIO is corrected with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
Change-Id: I98628ade3a1e19730ca6e6b4a63c28e6816176ce
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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We need to reduce the eMMC bus speed for these Apollo Lake mainboards
because of a limitation on Intel side for industry use cases.
Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Switch the default clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch enables TPM on SPI and adds the needed devicetree entry for
mc_apl5.
TEST=Build coreboot for mc_apl5 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: Iafc967c7a2bfee9bdb9b6591d12328620e2887cc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33173
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because of some differences to the baseboard this board variant needs
its own GPIO table.
Change-Id: Ie3424cb0b867c5d43cd7db9e9ae654196cef5e90
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Due to PCB limitations the SD-Card interface is not able to operate
with the highest frequency reliably. The OS driver will switch to
the highest mode if a SD-Card is attached which supports this high
frequency mode. In order to work around this PCB limitation disable the
high frequency modes in the controller capabilities (SDR104 and HS400
mode) and leave SDR50 and DDR50 enabled.
Change-Id: Ia5fed5fb70b027de34170b49620927614a00fb7a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The external RTC was removed on the mainboard as it is not needed.
Remove the usage of the driver for RX6110SA as well.
Change-Id: Ia476e58c0b0f343d4e9e4fa6039bf82b194a87d3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
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With commit
'4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)'
FSP is now requested to switch off HDA PCI device if it is disabled in
devicetree. Doing so results in a warm restart. Normally this event
will be stored in CMOS RAM (if the descriptor is configured to do so)
and therefore no further resets are requested by FSP on the next boots
as long as CMOS RAM is kept alive.
The Siemens mainboards based on Apollo Lake do not have a CMOS battery
and therefore the CMOS is not backed up. This leads to reset requests
from FSP after PCI enumeration on every boot. To avoid this reset enable
HDA in devicetree for these mainboards. Though we do not have any usage
of HDA it should not be an issue that the HDA device is now enabled. The
benefit is though that no reset is requested anymore by FSP.
Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no device on I2C0 which requires a lower clock rate.
Change-Id: Iaf01be5ea4839c54eb2f0ba95bca272970c24bdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch provides a clock on Pin PMU_SUSCLK. This is necessary for correct
function of the SMARC module.
Test=mc_apl4 flashed, booted into Linux, ckecked CLK with scope
Change-Id: Ieb1d66b5a09363c9bed2b19e7a204f206ee04158
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32168
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I380ffe1348731b8c84855047e057365bec94a08c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: I58ecd95a8427eba87611dd8ea4616aedbb1d01c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Fixes indirect includes that would break with followup work.
Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch enables TPM2 on LPC and adds the needed devicetree entry for
TPM for mc_apl4.
Test=mc_apl4 flashed, booted into Linux and checked via dmesg if TPM is
present
Change-Id: I9af7e1a8623302eca46f5ecd8e498678ccda92ad
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Remove a double entry for LPC device from devicetree.
Change-Id: Ib5b4f760251236d6a8b4aba719666daa97e7813d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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These boards need a working VTD therefore enable this feature.
Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected.
By removing this entry from devicetree, the default value (quiet mode)
is used. The problem is described in Intel document 334820-007 under
point APL47.
Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31138
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie0e11b1ce6c6acb1b74ce1196304f7e6ac4664d9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The TPM chip is connected to the SPI interface of APL. The proper chip
select pin needs to be used in order to access the TPM in the memory
mapped space. This needed chip select is internally (inside APL)
routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to
make the TPM work on SPI bus.
TEST=Build coreboot for mc_apl2 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This mainboard uses SOC internal UART 1 instead of UART 2 like all other
mc_apl1 mainboards.
Change-Id: Ib986962ed068fee019ffcec0391d43d5ab178458
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enaebl the RTC driver to be used on mc_apl4.
Change-Id: Ib8d2a9f6b8cea47cd10db4dfcc59eec1b21c7993
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Enable PTN3460 chip initialization to get LVDS attached LCD working on
mc_apl4.
Change-Id: I3ccf5398f16831db321eba846d6b041daadf31dd
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Add GPIO configuration to match the hardware of mc_apl4.
Change-Id: Ia69603f42c57c1cc682550b8eeeab42fbac27563
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30128
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29882
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is an on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This mainboard also has a SD slot.
Change-Id: I969e8ecb27aee4c8be212e67dfe6bd807ecd3b2f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This mainboard has four connected PCIe devices. The required root ports
are switched on and configured.
Change-Id: I82b13e1d245a172762ebd689ae136a762027033f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29810
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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An additional read of PTN configuration data at the end of the
ptn3460_init function is not necessary.
Change-Id: I5f7f647242e94b1af13757d00e80ed9813d435d0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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