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2560p
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broadwell_refcode
e6230
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Some coreboot project code with my work
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siemens
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mc_apl1
Age
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Author
2018-11-12
siemens/mc_apl4: Enable SDCARD
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove external RTC from I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Enable all PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Remove the correction of the Tx signal for SATA
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
Mario Scheithauer
2018-11-07
siemens/mc_apl4: Add new mainboard variant mc_apl4
Mario Scheithauer
2018-11-07
siemens/mc_apl2: Adjust GPIO settings for mc_apl2
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable I2C7 over devicetree
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Enable all PCIe root ports
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Adjust GPIO settings for mc_apl3
Mario Scheithauer
2018-10-30
siemens/mc_apl3: Add new mainboard variant mc_apl3
Mario Scheithauer
2018-10-08
Move compiler.h to commonlib
Nico Huber
2018-10-06
soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD
Furquan Shaikh
2018-10-04
mc_apl1: Set up SPI OPCODE menu before locking
Werner Zeh
2018-10-01
siemens/mc_apl1: Activate clock spreading for PTN3460
Mario Scheithauer
2018-09-27
siemens/mc_apl1: Add new mainboard variant mc_apl2
Mario Scheithauer
2018-09-27
siemens/mc_apl1: Make the DDR memory swizzle data configurable
Mario Scheithauer
2018-08-31
siemens/mc_apl1: Correct the Tx signal from SATA interface
Mario Scheithauer
2018-08-28
siemens/mc_apl1: Extend circuit life by clock gating and power gating
Mario Scheithauer
2018-08-27
siemens/mc_apl1: Disable PCI clock outputs on XIO bridge
Mario Scheithauer
2018-08-24
siemens/mc_apl1: Select DDR50 mode for eMMC
Mario Scheithauer
2018-08-23
siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard
Mario Scheithauer
2018-08-23
siemens/mc_apl1: Move board specific things to mc_apl1 variant
Mario Scheithauer
2018-06-06
soc/intel/common/block: Add common chip config block
Subrata Banik
2018-05-08
mb/siemens: Get rid of device_t
Elyes HAOUAS
2018-04-27
siemens/mc_apl1: Move board specific things to mc_apl1 variant
Mario Scheithauer
2018-04-26
siemens/mc_apl1: Provide baseboard and variant concepts
Mario Scheithauer
2018-04-24
compiler.h: add __weak macro
Aaron Durbin
2018-04-13
siemens/mc_apl1: Fix accuracy issue with IDT PMIC
Mario Scheithauer
2018-04-11
siemens/mc_apl1: Make DRAM configuration more flexible
Mario Scheithauer
2018-03-16
soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array
Furquan Shaikh
2017-11-07
siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY
Mario Scheithauer
2017-11-03
siemens/mc_apl1: Enable I2C0 with 100kHz
Mario Scheithauer
2017-11-03
siemens/mc_apl1: Set coreboot ready LED
Mario Scheithauer
2017-11-03
siemens/mc_apl1: Add legacy IRQ routing for PCI devices
Mario Scheithauer
2017-09-26
Use stopwatch_wait_until_expired where applicable
Jonathan Neuschäfer
2017-09-21
siemens/mc_apl1: Move SCI to IRQ 10
Mario Scheithauer
2017-09-14
siemens/mc_apl1: Add delay to wait for legacy devices
Werner Zeh
2017-09-08
siemens/mc_apl1: Disable internal UARTs
Mario Scheithauer
2017-09-08
siemens/mc_apl1: Set bus master bit for on-board PCI device
Mario Scheithauer
2017-08-18
include/device: Split i2c.h into three
Nico Huber
2017-08-15
soc/intel/common/block: Add LPC Common code and use it for APL
Ravi Sarawadi
2017-07-27
siemens/mc_apl1: Select skip RAPL configuration
Mario Scheithauer
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