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path: root/src/mainboard/siemens/mc_apl1
AgeCommit message (Expand)Author
2019-04-04siemens/mc_apl4: Provide CLK on APL Pin PMU_SUSCLKUwe Poeche
2019-03-21mb/siemens/mc_apl1: use comment in Kconfig.nameThomas Heijligen
2019-03-15mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>'Elyes HAOUAS
2019-03-06mb/siemens/{mc_apl1,mc_tcu3}: Fix typo on "Display"Elyes HAOUAS
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
2019-03-04arch/io.h: Add missing includesKyösti Mälkki
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
2019-02-13siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4Uwe Poeche
2019-02-13siemens/mc_apl2: Remove double entry from devicetreeMario Scheithauer
2019-02-05mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5Werner Zeh
2019-01-30siemens/mc_apl2: Change SERIRQ modeMario Scheithauer
2019-01-30siemens/mc_apl2: Correct whitespace of devicetreeMario Scheithauer
2019-01-30siemens/mc_apl2: Activate TPM supportMario Scheithauer
2019-01-16siemens/mc_apl4: Change UART_FOR_CONSOLE indexMario Scheithauer
2019-01-11siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer
2018-12-17siemens/mc_apl4: Enable RTC RX6110SA on this mainboardUwe Poeche
2018-12-17siemens/mc_apl4: Enable LVDS Display on mc_apl4Uwe Poeche
2018-12-17siemens/mc_apl4: Add GPIO configurationUwe Poeche
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
2018-11-29siemens/mc_apl5: Disable PCI clock outputs on XIO bridgesMario Scheithauer
2018-11-29siemens/mc_apl5: Set bus master bit for on-board PCI deviceMario Scheithauer
2018-11-29siemens/mc_apl5: Enable SDCARDMario Scheithauer
2018-11-27siemens/mc_apl5: Adjust the settings for the PCIe root portsMario Scheithauer
2018-11-26siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN readMario Scheithauer
2018-11-23siemens/mc_apl4: Set CPU clock to minimum ratioWerner Zeh
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
2018-11-18siemens/mc_apl5: Add new mainboard variant mc_apl5Mario Scheithauer
2018-11-16mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VARElyes HAOUAS
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
2018-11-16mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov
2018-11-16siemens/mc_apl4: Clean up ramstageMario Scheithauer
2018-11-16siemens/mc_apl4: Overwrite swizzle data for LPDDR4Mario Scheithauer
2018-11-12siemens/mc_apl4: Enable SDCARDMario Scheithauer
2018-11-12siemens/mc_apl4: Remove external RTC from I2C0Mario Scheithauer
2018-11-12siemens/mc_apl4: Enable all PCIe root portsMario Scheithauer
2018-11-12siemens/mc_apl4: Remove reduced clock rate for I2C0Mario Scheithauer
2018-11-12siemens/mc_apl4: Disable CLKREQ of PCIe root portsMario Scheithauer
2018-11-12siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer
2018-11-12siemens/mc_apl3: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
2018-11-12siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer
2018-11-12siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer
2018-11-12siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
2018-11-07siemens/mc_apl4: Add new mainboard variant mc_apl4Mario Scheithauer
2018-11-07siemens/mc_apl2: Adjust GPIO settings for mc_apl2Mario Scheithauer
2018-11-07siemens/mc_apl3: Disable I2C7 over devicetreeMario Scheithauer
2018-11-07siemens/mc_apl3: Enable all PCIe root portsMario Scheithauer
2018-11-07siemens/mc_apl3: Remove reduced clock rate for I2C0Mario Scheithauer
2018-11-07siemens/mc_apl3: Disable CLKREQ of PCIe root portsMario Scheithauer
2018-11-07siemens/mc_apl3: Adjust GPIO settings for mc_apl3Mario Scheithauer
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