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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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siemens
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mc_apl1
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Author
2018-12-17
siemens/mc_apl4: Enable LVDS Display on mc_apl4
Uwe Poeche
2018-12-17
siemens/mc_apl4: Add GPIO configuration
Uwe Poeche
2018-11-30
cpu/intel/common: Use a common acpi/cpu.asl file
Arthur Heymans
2018-11-29
siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-29
siemens/mc_apl5: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-29
siemens/mc_apl5: Enable SDCARD
Mario Scheithauer
2018-11-27
siemens/mc_apl5: Adjust the settings for the PCIe root ports
Mario Scheithauer
2018-11-26
siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read
Mario Scheithauer
2018-11-23
siemens/mc_apl4: Set CPU clock to minimum ratio
Werner Zeh
2018-11-23
mb: Set coreboot as DSDT's manufacturer model ID
Elyes HAOUAS
2018-11-21
ACPI: Fix DSDT's revision field
Elyes HAOUAS
2018-11-18
siemens/mc_apl5: Add new mainboard variant mc_apl5
Mario Scheithauer
2018-11-16
mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VAR
Elyes HAOUAS
2018-11-16
src: Remove unneeded include <lib.h>
Elyes HAOUAS
2018-11-16
mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree
Peter Lemenkov
2018-11-16
siemens/mc_apl4: Clean up ramstage
Mario Scheithauer
2018-11-16
siemens/mc_apl4: Overwrite swizzle data for LPDDR4
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Enable SDCARD
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove external RTC from I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Enable all PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Remove the correction of the Tx signal for SATA
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
Mario Scheithauer
2018-11-07
siemens/mc_apl4: Add new mainboard variant mc_apl4
Mario Scheithauer
2018-11-07
siemens/mc_apl2: Adjust GPIO settings for mc_apl2
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable I2C7 over devicetree
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Enable all PCIe root ports
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-07
siemens/mc_apl3: Adjust GPIO settings for mc_apl3
Mario Scheithauer
2018-10-30
siemens/mc_apl3: Add new mainboard variant mc_apl3
Mario Scheithauer
2018-10-08
Move compiler.h to commonlib
Nico Huber
2018-10-06
soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD
Furquan Shaikh
2018-10-04
mc_apl1: Set up SPI OPCODE menu before locking
Werner Zeh
2018-10-01
siemens/mc_apl1: Activate clock spreading for PTN3460
Mario Scheithauer
2018-09-27
siemens/mc_apl1: Add new mainboard variant mc_apl2
Mario Scheithauer
2018-09-27
siemens/mc_apl1: Make the DDR memory swizzle data configurable
Mario Scheithauer
2018-08-31
siemens/mc_apl1: Correct the Tx signal from SATA interface
Mario Scheithauer
2018-08-28
siemens/mc_apl1: Extend circuit life by clock gating and power gating
Mario Scheithauer
2018-08-27
siemens/mc_apl1: Disable PCI clock outputs on XIO bridge
Mario Scheithauer
2018-08-24
siemens/mc_apl1: Select DDR50 mode for eMMC
Mario Scheithauer
2018-08-23
siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard
Mario Scheithauer
2018-08-23
siemens/mc_apl1: Move board specific things to mc_apl1 variant
Mario Scheithauer
2018-06-06
soc/intel/common/block: Add common chip config block
Subrata Banik
2018-05-08
mb/siemens: Get rid of device_t
Elyes HAOUAS
2018-04-27
siemens/mc_apl1: Move board specific things to mc_apl1 variant
Mario Scheithauer
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