index
:
coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
vimacs
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mainboard
/
siemens
/
sitemp_g1p1
/
romstage.c
Age
Commit message (
Expand
)
Author
2014-07-08
mainboard: Trivial - drop trailing blank lines at EOF
Edward O'Callaghan
2014-05-28
mainboard/*: Convert to generic ITE superio romstage component
Edward O'Callaghan
2014-05-11
superio/ite/*: Factor out generic romstage component
Edward O'Callaghan
2014-05-03
Drop useless mainboard-romstage defines
Patrick Georgi
2014-01-27
sitemp-g1p1: Migrate to new cmos.default approach
Vladimir Serbinenko
2013-12-26
AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes
Kyösti Mälkki
2013-12-26
AMD boards (non-AGESA): Cleanup earlymtrr.c includes
Kyösti Mälkki
2013-08-15
Include boot_cpu.c for romstage builds
Kyösti Mälkki
2013-03-22
x86: Unify arch/io.h and arch/romcc_io.h
Stefan Reinauer
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2012-11-28
amdk8/amdfam10: Use CAR_GLOBAL for sysinfo
Patrick Georgi
2012-11-27
Remove AMD special case for LAPIC based udelay()
Patrick Georgi
2012-11-19
siemens/sitemp_g1p1: Drop copy of cmos checksum calculation
Patrick Georgi
2012-11-14
mainboard/siemens/sitemp_g1p1: Fix CMOS checksum algorithm here, too
Nico Huber
2012-05-08
Clean up #ifs
Patrick Georgi
2011-11-01
remove trailing whitespace
Stefan Reinauer
2011-05-13
siemens/sitemp_g1p1: Adapt read_option() to latest changes
Josef Kellermann
2011-05-12
Remove uart_init() in Siemens sitemp-g1p1
Patrick Georgi
2011-05-11
Add Siemens SITEMP-G1 board
Josef Kellermann