index
:
coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
vimacs
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mainboard
/
siemens
Age
Commit message (
Expand
)
Author
2019-03-12
src: Drop unused 'include <arch/acpigen.h>'
Elyes HAOUAS
2019-03-08
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2019-03-07
src: Drop unused include <timestamp.h>
Elyes HAOUAS
2019-03-06
src: Drop unused include <arch/acpi.h>
Elyes HAOUAS
2019-03-06
mb/siemens/{mc_apl1,mc_tcu3}: Fix typo on "Display"
Elyes HAOUAS
2019-03-04
device/mmio.h: Add include file for MMIO ops
Kyösti Mälkki
2019-03-04
arch/io.h: Drop unnecessary include
Kyösti Mälkki
2019-03-04
arch/io.h: Add missing includes
Kyösti Mälkki
2019-03-01
device/pci: Fix PCI accessor headers
Kyösti Mälkki
2019-03-01
mb/siemens/mc_bdx1: Enable TPM2 on LPC
Werner Zeh
2019-02-13
siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4
Uwe Poeche
2019-02-13
siemens/mc_apl2: Remove double entry from devicetree
Mario Scheithauer
2019-02-05
mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5
Werner Zeh
2019-01-30
siemens/mc_apl2: Change SERIRQ mode
Mario Scheithauer
2019-01-30
siemens/mc_apl2: Correct whitespace of devicetree
Mario Scheithauer
2019-01-30
siemens/mc_apl2: Activate TPM support
Mario Scheithauer
2019-01-16
siemens/mc_apl4: Change UART_FOR_CONSOLE index
Mario Scheithauer
2019-01-11
siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLE
Mario Scheithauer
2019-01-06
device: Use pcidev_on_root()
Kyösti Mälkki
2018-12-28
arch/x86: Drop spurious arch/stages.h includes
Kyösti Mälkki
2018-12-19
mainboard: Remove useless include <device/pci_ids.h>
Elyes HAOUAS
2018-12-17
siemens/mc_apl4: Enable RTC RX6110SA on this mainboard
Uwe Poeche
2018-12-17
siemens/mc_apl4: Enable LVDS Display on mc_apl4
Uwe Poeche
2018-12-17
siemens/mc_apl4: Add GPIO configuration
Uwe Poeche
2018-11-30
cpu/intel/common: Use a common acpi/cpu.asl file
Arthur Heymans
2018-11-29
siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-29
siemens/mc_apl5: Set bus master bit for on-board PCI device
Mario Scheithauer
2018-11-29
siemens/mc_apl5: Enable SDCARD
Mario Scheithauer
2018-11-28
mb/*/*/Kconfig: Remove useless comment
Elyes HAOUAS
2018-11-27
siemens/mc_apl5: Adjust the settings for the PCIe root ports
Mario Scheithauer
2018-11-26
siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read
Mario Scheithauer
2018-11-23
siemens/mc_apl4: Set CPU clock to minimum ratio
Werner Zeh
2018-11-23
mb: Set coreboot as DSDT's manufacturer model ID
Elyes HAOUAS
2018-11-21
ACPI: Fix DSDT's revision field
Elyes HAOUAS
2018-11-18
siemens/mc_apl5: Add new mainboard variant mc_apl5
Mario Scheithauer
2018-11-16
mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VAR
Elyes HAOUAS
2018-11-16
src: Remove unneeded include <cbfs.h>
Elyes HAOUAS
2018-11-16
src: Remove unneeded include <lib.h>
Elyes HAOUAS
2018-11-16
mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree
Peter Lemenkov
2018-11-16
siemens/mc_apl4: Clean up ramstage
Mario Scheithauer
2018-11-16
siemens/mc_apl4: Overwrite swizzle data for LPDDR4
Mario Scheithauer
2018-11-12
src: Remove unneeded include "{arch,cpu}/cpu.h"
Elyes HAOUAS
2018-11-12
siemens/mc_apl4: Enable SDCARD
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove external RTC from I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Enable all PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Remove reduced clock rate for I2C0
Mario Scheithauer
2018-11-12
siemens/mc_apl4: Disable CLKREQ of PCIe root ports
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
Mario Scheithauer
2018-11-12
siemens/mc_apl3: Set bus master bit for on-board PCI device
Mario Scheithauer
[prev]
[next]