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path: root/src/mainboard/siemens
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2017-04-10nb/amdk8/(pre_)f.h: Don't declare global variable in headerArthur Heymans
This is needed if one wants to use the header more than once. Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19029 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-04-04siemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge ICMario Scheithauer
This mainboard uses a LVDS connection for LCD panels. Apollo Lake SoC provides a display controller with three independent pipes (1x eDP and 2x DP/HDMI). PTN3460 is an embedded DisplayPort to LVDS bridge device that enables connectivity between an eDP source and LVDS display panel (http://www.nxp.com/documents/data_sheet/PTN3460.pdf). The bridge contains an On-chip Extended Display Identification Data (EDIT) emulation for EDIT data structures. This patch sets up PTN3460 to be used with the appropriate LCD panel. Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-29siemens/mc_apl1: Adjust gpio settingsMario Scheithauer
Adjust gpio settings according to the hardware layout. Change-Id: I2f440e863c2e6f59298c500ac5aefa3b7386bcdf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18995 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-03-21mainboards: Don’t select `CONSOLE_POST`Paul Menzel
Currently, it’s impossible for the user to select `NO_POST`, for boards selecting `CONSOLE_POST` in their config. ``` warning: (BOARD_SPECIFIC_OPTIONS) selects CONSOLE_POST which has unmet direct dependencies (VENDOR_SIEMENS && BOARD_SIEMENS_MC_BDX1 || !NO_POST) ``` This is currently done for Intel Camelback Mountain and Siemens MC-BDX1. Selecting the option `CONSOLE_POST` in board specific configuration is not a good idea, as this should be user configurable over Kconfig, and also the tree-wide defaults should be the same for these options. Kconfig is different, as commit 97535558f1 (mainboard/{google,intel}: Change config option selection) only touch the Intel board. Change-Id: I91c1e0cb92ed218b6bbc7c33759b91f748cf6f51 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18878 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-03-15siemens/mc_apl1: Clean up the codeMario Scheithauer
This patch make some general adaptations in relation to commit 6a489237 (mainboard/intel/leafhill: Clean up). - add necessary defaults to Kconfig - remove irrelevant entries from FMD file - include romstage file for better understanding Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18808 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-20siemens/mc_apl1: Set MAC address for all available i210 MACsMario Scheithauer
This mainboard uses two i210 Ethernet controller. Therfore we enable the usage of the i210 driver and have to provide a function to search for a valid MAC address for all i210 devices by using Siemens hwilib. Change-Id: I36246cdef987fcece15a297ebb2f41561fca1f69 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18380 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-02-15siemens/mc_apl1: Make basic settings for booting the mainboardMario Scheithauer
This commit makes a basic adjustment for GPIOs, device tree, flash map and MRC settings. With these basic settings the mainboard boots into Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow. Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18292 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-02-02siemens/mc_apl1: Add new mainboardMario Scheithauer
This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MC APL1 mainboard will follow in separate commits. Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
2017-01-13fsp_baytrail: Enable graphic init per defaultWerner Zeh
Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni@kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/18109 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-26amd-based mainboards: Fix whitespace in _PTS commentsMarshall Dawson
Correct tabs that were intended as spaces. Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17905 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-12-06cpu/amd/mtrr.h: Drop excessive includesKyösti Mälkki
Change-Id: Id404bdab1f2361f1e7d20f7ee72111971863dddf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17736 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/cpu.h: Drop excessive includesKyösti Mälkki
Change-Id: Ifeef04b68760522ce7f230a51f5df354e6da6607 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17734 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Move SMM prototypes under x86Kyösti Mälkki
Change-Id: Iefbc17dcfcf312338d94b2c2945c7fac3b23bff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17732 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-06mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missingWerner Zeh
Do not abort the initialization of PTN3460 if HW-ID could not be retrieved and just assume that the HW-ID does not match 7.9.2.0. In this case PTN3460 will be setup to a working condition even if this field is missing. This makes this driver more robust with faulty blocks. Change-Id: I301fb165a7924768e44182d92be820294beb0280 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/17671 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-11-24mc_tcu3: Swap LVDS even and odd lanes for a certain hardwareWerner Zeh
Due to some LVDS cable constraints even and odd lanes needs to be swapped on certain hardware. The hardware ID will be used to distinguish between these two cases. The swapping itself will be done by PTN3460, which is configurable for that. Change-Id: I339b2321a8ed1bc3bbf10aa8e50eb598b14b15fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/17576 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-11-21mb/siemens/sitemp_g1p1/cmos.layout: Re-add cmos_defaults_loadedNico Huber
I guess it was dropped because its concept was misunderstood. The idea is to always have it set to `Yes` in the cmos.default. Users can then ack the loading of the defaults by setting it to `No`. If the defaults ever get loaded again, they'll be notified by the default `Yes`. Change-Id: I1aa6d75bd5aa153c7b11a6b74564272eaa7cc523 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17355 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-05siemens/mc_tcu3: Increase LCD backlight turn-on delay to 500 msWerner Zeh
Due to different LCD panel requirements the delay between LVDS becomes active and the backlight is switched on needs to be increased to 500 ms. Change-Id: I09029624469aef412141c7b46224d48557ba4af1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16875 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-04mainboard/siemens/sitemp_g1p1: Use tabs for indentsElyes HAOUAS
Change-Id: Ia5ea2198cdc93822723a4fe5440d574d76cb4de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16847 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01mainboard/*/*/*/usb.asl: Use tabs for indentsElyes HAOUAS
Change-Id: Id46a0c4ca59dc7224c2eedd674ea3a5486509de1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16824 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-26mainboard/*/*/dsdt.asl: Use tabs for indentsElyes HAOUAS
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26mainboard/*/*/mptable.c: Improve code formattingElyes HAOUAS
Change-Id: I341293cd334d6d465636db7e81400230d61bc693 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/lenovo-winent: Add space around operatorsElyes HAOUAS
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-12siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPCWerner Zeh
Since this mainboard provides 4 COM ports on LPC, enable decoding of the corresponding addresses using the generic LPC decode registers. Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16535 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01siemens/sitemp_g1p1: Fix typoPatrick Georgi
Change-Id: I1c9af223d3598c4822905acce0cf9b1dca6ad1b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1287066 Reviewed-on: https://review.coreboot.org/15981 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-07-31mainboard: Format irq_tables.cPaul Menzel
Run the command below to format the files `irq_tables.c` of (mostly AMD) mainboards correctly with GNU indent 2.2.10. ``` $ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l ``` Fix up the following two checkpatch.pl errors manually. ``` ERROR: that open brace { should be on the previous line #1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129: + uint8_t reg[8] = + { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 }; ERROR: that open brace { should be on the previous line #1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131: + uint8_t irq[8] = + { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 }; ``` This is needed, so that follow-up commits, fixing checkpatch.pl errors and warnings, won’t run into conflicts with the git commit hooks, when for example, spaces instead of tabs are used for indentation. Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15932 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31Update degree symbol to utf-8 encoding in commentsMartin Roth
Almost all of the places where we have the degree symbol '°', it's encoded as 0xc2 0xb0 (utf-8 encoding). There are a few places where it is encoded as just a high ascii byte: 0xb0. Editors that support the high ascii 0xb0 seem to support the utf-8 0xc2 0xb0 encoding as well, but the opposite does not seem to be true. Change the high-ascii degree symbols to utf-8 encoding. Change-Id: I3d06289b802f45e938dc72b4c437fca56235b62b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15978 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-14siemens/mc_bdx1: Add usage of external RTC PCF8523Werner Zeh
This mainboard contains an external RTC chip PCF8523. Enable usage of this chip and add some initialization values to device tree. Change-Id: I25c0a017899ee904f3aa02bdc7dcaf61dee67e3a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15642 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-08siemens/mc_bdx1: Move SCI to IRQ 10Werner Zeh
IRQ 9 is used for different purpose on this board so move SCI away to IRQ10. Change-Id: I107bfb5ec8cd05f844ee75550779be7746e77a88 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15563 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-07siemens/mc_bdx1: Set up opcode menu for SPI controllerWerner Zeh
Since SPI controller opcode registers are locked by FSP, they need to be initialized to a known good state before ReadyToBoot event and after every SPI flash access (e.g. for MRC cache) has been finished in order to enable the OS to use SPI controller without constraints. Change-Id: I0a66344cd44e036c3999ae98d539072299cf5112 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15547 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-06siemens/mc_bdx1: Add usage of Siemens NC FPGA driverWerner Zeh
Enable NC FPGA driver for this mainboard. Change-Id: I87b6b10038f3d161a25b2008b7ea44b5627cca43 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15545 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-05siemens/mc_bdx1: Set up MAC address for available i210 MACsWerner Zeh
Enable the usage of DRIVER_INTEL_I210 and provide a function to search for a valid MAC address for all i210 devices using hwilib. Change-Id: Ic0f4f1579364cf5b0111334a05a8a0926785318b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-05intel/i210: Change API for function mainboard_get_mac_address()Werner Zeh
The function mainboard_get_mac_address() is used to get a MAC address for a given i210 PCI device. Instead of passing pure numbers for PCI bus, device and function pass the device pointer to this function. In this way the function can retrieve the needed values itself as well as have the pointer to the device tree so that PCI path can be evaluated there. Change-Id: I2335d995651baa5e23a0448f5f32310dcd394f9b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15516 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-10siemens/mc_tcu3: Don't try to init unsupported panel typeWerner Zeh
The LCD panel type is read using 4 GPIOs. Of these 16 possible combinations only 5 are supported right now. If the GPIO setting encodes an unsupported panel type, there will be no matching hwinfo.hex in cbfs. Therefore it makes no sense to try to initialize the DisplayPort-2-LVDS converter. Leave the function instead in this case. Change-Id: If8c67a3f5be762758d516c4939dd1de4ff1c8ba5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14743 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-05-09siemens/mc_tcu3: Fix spelling of *set up*Paul Menzel
The verb *set up* is written with a space [1]. So correct that in the function descriptions. [1] http://www.merriam-webster.com/dictionary/set%20up Change-Id: Icf5aa7eca2c379fdf7ff1935d71efc347f5ce6fa Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/14701 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09siemens/mc_tcu3: Add blank lines for better legibilityPaul Menzel
Change-Id: I6d1200dd59e53ca892594c1fce784639a9817550 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/14700 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09siemens/mc_tcu3: Remove unneeded variable assignmentPaul Menzel
Assigning the value `1` to `status` in the default branch of the switch statement is not needed, as the stored value is overwritten before it can be used. Change-Id: I532b0e217ff4ed315cd30b08d339c755c6df7539 Found-by: Coverity, CID 1355008: Code maintainability issues (UNUSED_VALUE)) Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/14699 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-29siemens/mc_bdx1: Add new mainboard.Werner Zeh
Add new mainboard for MC BDX1 board which is based on Intel Camelback Mountain. This mainboard is an industry type board and has several Ethernet interfaces among with two USB3.0 connectors. It uses 24V DC power supply and has its own form factor which does not match any standard. This commit adds the new mainboard and prepares the Kconfig environment so that this board can be selected and generated. Although the generated image can boot into Linux and DOS, not all functions are implemented yet. Forthcoming commits will add more functionality. Change-Id: I29011cfd3b0d13bcf163223f657e02f69978e39a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14516 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
2016-04-28drivers/intel/i210: Use uint8_t and friends instead of u8Werner Zeh
Switch all types to uint8_t and the like instead of u8. Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14515 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28mc_tcu3: Switch to hwilib instead of own hwinfo implementationWerner Zeh
Use hwilib in vendorcode/siemens/hwilib to get fields from hwinfo instead of having mainboard specific hwinfo code. This patch does not change the functional behavior in any way. Change-Id: Idb226a82a08b1b753f654c5cde106236e72f33c3 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14506 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-25mc_tcu3: Enable graphic init codeWerner Zeh
The used Baytrail-M SoC on TCU3 tend to have issues with DisplayPort if the graphic power gate is not set up in coreboot. To avoid this error, use the graphic init code on this board. Change-Id: I973bbaa7d86c1ede1f2884b3a08ccb31f7d85087 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13774 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-02src/: Fix Kcofig symbols missing CONFIG_ prefixMartin Roth
- Add CONFIG_ prefix to two symbols. - Remove the use of the third symbol as it will never be matched. Change-Id: Ifa7f6884001cb05fb8397f193c4b08a0161f498c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13539 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-25mc_tcu3: Enable auto generated attributes in cbfsWerner Zeh
Use CBFS_AUTOGEN_ATTRIBUTES for mc_tcu3 to enable position and alignment attributes in cbfs. Change-Id: I6c39bb02ab641d7e22e20e77a72a577f159549dd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13123 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-12-18siemens/mc_tcu3: Set GPIO_S0_SC[75] to outputWerner Zeh
The usage of the pin has changed and therefore this pin needs to be set up as output and drive low initially. Change-Id: Ie3eb9cc703f7f73d59fad52ea9e514997d84606a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12754 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-16intel/fsp_baytrail: rename include folder baytrail to include/socBen Gardner
This is to match the layout of the non-fsp baytrail to make comparisons easier and possibly remove duplicate files. Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12686 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-16southbridge/amd/sb600: Update HPET base address with #defineMartin Roth
The SB600 code had the base address of the HPET hardcoded throughout. It looks like the plan was to have it be updated in ACPI if needed, but this wasn't ever implemented. The variable names being used to do this update were the same, causing an IASL warning. Because of this, the operation to update the HPET address actually did nothing. This was fine, because it didn't actually need to be updated. - Replace all that code with a #define. - Add and update some comments in the same area. Fixes IASL warning: dsdt.aml 1505: Store(HPBA, HPBA) Warning 3023 - ^ Duplicate value in list (Source is the same as Target) Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 10:54:30 +0000