coreboot - Some coreboot project code with my work

Age	Commit message (Collapse)	Author
2019-09-23	mb/up/squared: Fill LPDDR4 dimm info	Patrick Rudolph
	Fill the dimm info struct to make SMBIOS type 17 appear. TESTED=Up Squared Change-Id: I4de63362c8fea8a886594cdcf0eec48421afb605 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34564 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16	mb/up/squared: Do RAM config based on SKU ID	Felix Singer
	TESTED=UP Squared Change-Id: Ic121652213d5b1f65cff2f3096e919a3cf88db72 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34838 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-06	src/mainboard/up/squared: Add Support for iTPM	Christian Walter
	Add support for the integrated TPM in Kconfig and update device tree. Change-Id: I3a51545c493674aeed9aef72db24f77315d033ce Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-13	mb/up/squared: Enable Vtd	Felix Singer
	Change-Id: Ie935f98f84772a53de92f0dd2d13a381f5dbaf89 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-01	mb/up/squared: Add kernel cmdline parameters	Felix Singer
	Since ttyS0 isn't used for UART0, configure ttyS4 as default Change-Id: Ia0469226253b08328807d5401c05633296e43d22 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33785 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-27	mb/upsquared: Align partitions to 4KiB	Felix Singer
	This fixes warnings while booting coreboot. Change-Id: If1e99b74ded5f743a3ad4fc829ae9747276c483a Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33784 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-26	mb/up/squared: Remove unnecessary code	Felix Singer
	This patch removes unnecessary code which configures default FSP values. Change-Id: If7dae4f24a9fcb01d2d47063dd3a0f4ce6c120d2 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22	mb/up/squared: Add mainboard	Felix Singer
	Works: - bootblock, romstage, ramstage - Serial console UART0, UART1 - SPI flash console - iGPU init with libgfxinit - LAN1, LAN2 - USB2, USB3 - HDMI, DisplayPort - eMMC - flashing with flashrom externally WIP: - Documentation - VGA For some reason Seabios can not find the CBFS region and therefore it can't load seavgabios, but generally it is working as soon as Linux is booted. - ACPI Works not: - Devices needs proper configuration - Seabios can't find CBFS region Untested: - GPIO pin header - 60 pin EXHAT - Camera interface - MIPI-CSI2 2-lane (2MP) - MIPI-CSI2 4-lane (8MP) - SATA3 - USB3 OTG - embedded DisplayPort - M.2 slot - mini PCIe - flashing with flashrom internally using Linux Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>