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2016-12-22Combine Broadwell Chromeboxes using variant board schemeMatt DeVillier
Combine existing boards google/guado, rikku, and tidus using their common reference board google/jecht as a base. Additional changes besides simple consolidation include: - simplify power LED functions - simplify HDA verb definitions using azelia macros - use common SoC functions to generate FADT table - correct FADT table header version - remove unused haswell_pci_irqs.asl - remove unused header includes (various) - set sane default fan speed (0x4d) for all variants Variant setup modeled after google/beltino Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17913 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-22mb/asus/p5gc-mx: Add mainboardArthur Heymans
Tested to work: * GPU (Nvidia gt210) in PCIe x16 slot; * SATA; * serial; * 800MHz and 1067MHz FSB Core 2 Duo CPUs; * ethernet; * native VGA graphic init. What does not work: * resume from s3 suspend; * superio hardware monitor (not initialised in coreboot). Quirks: * does not boot with just one dimm in slot B. Change-Id: Ide5494be7f2f16d6b5cfd2ccf4ec438f0587add5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17558 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-22agesa and binaryPI mainboards: Fix devicetree hudson commentsMarshall Dawson
Make the ending comment associated with "chip ...hudson" match the appropriate directory name. Change-Id: I5e0d6d41a2e3f963760aad08ed6108acac5b66b3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17904 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-12-20mb/google/slippy: Hook up libgfxinitArthur Heymans
Both HDMI and eDP work (simultaneously). TESTED on Acer C720 (peppy). Change-Id: Ifc4e3c187bcabd8965d9586237a52b440bfa7f20 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17916 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-20mb/lenovo/x60: Remove PCI reset code from romstagePaul Menzel
Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit bc8613ec (Fix i945 based boards) fixes that to use the correct delay of 200 ms. This code was then copied over, when adding support for the Lenovo X60. The reset was related to the shipped crypto card on the Roda RK886EX and Kontron 986LCD-M, so is not needed on the Lenovo X60. So remove it. TEST=Build and boot on Lenovo X60t. Change-Id: Ia37d9f0ecf5655531616edb20b53757d5d47b42f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17703 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-20google/eve: Fix configuration of some GPIOsDuncan Laurie
GPP_D12 needs an internal pull-up to get this rail working on current boards. GPP_D0-GPP_D3 were changed from SPI interface and I just missed this change earlier. BUG=chrome-os-partner:58666 TEST=test camera and touchpad on eve Change-Id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17922 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19google/poppy: Add new boardFurquan Shaikh
Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-19amd/mainboard: Clean up bettong, gardenia USB todosMarshall Dawson
An incorrect board name was propagated over various generations of mainboards. Correct the comments for these. Addressing the todo items will come in a later patch. Change-Id: I4abd028fee5087955a7b6ba8d38f99c8207d24b4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17903 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2016-12-19motherboard/amd: Clean up bettong, gardenia makefilesMarshall Dawson
Declutter the conditional building of fchec.c. Use the CONFIG setting directly instead of ifeq (). Change-Id: I6d3721764e66e5615a639c1979d60ff1291b5d33 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17902 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2016-12-19amd/gardenia: Update ACPI routingMarshall Dawson
Reduce the Bettong devices and match up the comments to the northbridge. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from e7c38571be6406453640d671210b2074a91f162e) Change-Id: I53adff741f5cf2bd75c37421949bd30f214f5692 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17849 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-19pcengines/apu2: add board supportPiotr Król
Initial work based on db-ft3b-ls and code released by Eltan. Board boots with some limitation. Now the AGESA binary is harcoded and board specific until it's fixed by the SoC vendor. memtest86+ from external repo skips looking for SPD on SMBus, which when performed cause memtest86+ to hang. Still didn't tried whole test suit. SeaBIOS 1.9.3 have some problems with USB which lead to no booting in some cases. Full log: https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872 SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios) works fine. Those changes are planned for upstream. Information about obtaining and booting Voyage Linux: https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/14138 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-19amd/gardenia: Add AHB bridge registers in ACPIMarshall Dawson
Add the region used by the A-Link to AHB configuration registers. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (squashed from 2c8dafdf44cf1a84cbc25e8aa381c04c160ee705 and 3c755f70ffa36c0fc92a1da0e3f5f877c8dc9e8b) Change-Id: I7398452c6e70b4545e16398f3fec157f2f30293a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17848 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-19amd/gardenia: Add I2C devices to ACPIMarshall Dawson
Add the missing two I2C controllers. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from 0be00a96b9eb40c959a422a5ca4773d2353d244d) Change-Id: I3ea74a6c0472711102b19a7ca0209aaeeeb2d601 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17847 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-19amd/gardenia: Clean up GPIO ASLMarshall Dawson
Remove the unused Name field. Its previous design generates an FWTS error and a recommendation for changing it to Serialized. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 1d970f1aa16c647e56a08c83f5719041882a2fc0) Change-Id: I27748a4f84286e80043f516564ef64350ef3fef9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17846 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-18intel cache-as-ram: Move DCACHE_RAM_BASEKyösti Mälkki
Having same memory region set as both WRPROT and WRBACK using MTRRs is undefined behaviour. This could happen if we allow DCACHE_RAM_BASE to be located within CBFS in SPI flash memory and XIP romstage is at the same location. As SPI master by default decodes all of top 16MiB below 4GiB, initial cache-as-ram line fills may have actually read from SPI flash even in the case DCACHE_RAM_BASE was below the nominal 4GiB - ROM_SIZE. There are no reasons to have this as board-specific setting. Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-18emulation/qemu-q35: Increase default ROM_SIZEKyösti Mälkki
Larger size fits GRUB payload and fixes case to build 82801ix with HAVE_INTEL_FIRMWARE. Change-Id: I90e33fb3a0b0e1a60dcc2a9a022bef034f3270d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17830 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-17google/reef: Use exported GPIOs and ACPI regulator for touchscreenFurquan Shaikh
ELAN touchscreen device expects firmware to export GPIOs and ACPI regulators for managing power to the device. Thus, provide the required ACPI elements for OS driver to properly manage this device. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that touchscreen works properly on boot-up and after suspend/resume. Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16google/eve: Set throttle offset to 10 degreesDuncan Laurie
Set the thermal throttle (prochot) activation to be 10 degrees below TJmax so PROCHOT# kicks in at 90C instead of 100C. BUG=chrome-os-partner:58666 TEST=boot on eve, check msr value before and after resume: > iotools rdmsr 1 0x1a2 0x000000000a6400e6 > echo mem > /sys/power/state > iotools rdmsr 1 0x1a2 0x000000000a6400e6 Change-Id: I3ab3a050a1e27c18a940bd7519eabaf015ef93eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17901 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-16amd/gardenia: Enable LPC decodesMarshall Dawson
Turn on LPC decoding in romstage. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 5d9dae5a1fdab1bf6c418dc7e6de28069bd342dc) Change-Id: I937eb5c5b6c6a9f7a13ebd0bec7fcc8d789427ce Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17227 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Enable HD AudioMarshall Dawson
Add ALC286 commands and update the PLATFORM_CONFIGURATION structure with the list address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee) Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17226 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Update PCIe and DDI lanesMarshall Dawson
Change the Carrizo settings used for Bettong to ones specific to Stoney on Gardenia. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit e99b2c7e2c913413fdc83ad37c5519837a38c7fb) Change-Id: I4376421c8c08dab9d7ff1428993eed3978e89657 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17225 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Enable SATA controllerMarshall Dawson
Duplicate the code from DB-FT3lc and use the correct names. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 935cbe6e8b81f11291322dba3688b0a5a0c3291c) Change-Id: I3a3c62f09819ea02388bf70945fd0c011ad7555a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17224 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Update xHCI configurationMarshall Dawson
Remove a duplicated check and setting for xHCI during the AMD_INIT_RESET callout. This is handled by the wrapper. Also remove nearby commented code. EcChannel0 is not a member of FCH_RESET_DATA_BLOCK. Leave the check in AMD_INIT_ENV. Although AGESA honors what was previously requested, additional settings depend on the state of Usb.Xhci0Enable. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd) Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17223 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Configure GPIO signalsMarshall Dawson
Change the default configuration for the following settings: AGPIO14: BT radio disable AGPIO64: NFC PU AGPIO65: NFC wake AGPIO66: Webcam AGPIO69: PCIe presence detect AGPIO70: GPS sleep AGPIO116: MUX for Power Express Eval EGPIO119: SD power Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4) Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17222 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Remove board ID capabilityMarshall Dawson
Remove the last bit of Bettong board_id checking from Gardenia. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit b617823d1d2860a3f6d766a40ae95e5486739a5c) Change-Id: Ibc56dbbfa1b15b21ebadb9f6c9c54936566a2986 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17221 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Remove rev-specific storage setupMarshall Dawson
Gardenia doesn't have the ability to modify settings depending on the board ID. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 536b4c424e5259ddbd82469f5f426d3189ff3f89) Change-Id: I2c928431306c669735cf735042855e95721bb107 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17220 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Correct SPD AGESA calloutMarshall Dawson
Gardenia makes no special considerations for a board_id regarding SPD access and addressing. Remove this from the source and use the standard AGESA call. Make SPD address changes to devicetree.cb. Note that Gardenia is designed to be a two channel, single DIMM/channel system (some SKUs with two DIMMs on the second channel). However, this port is for the Stoney processor which is a single channel. As a result, the second DIMM slot is not usable. A future improvement could involve a port using a different processor, with unique devicetree files for each. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15) Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17219 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16mainboard/amd: Copy bettong to gardenia and update for buildMarc Jones
Use bettong as the reference for the gardenia mainboard. Update makefiles etc so it builds. This patch intentionlly keeps the carrizo_fch.asl file to remain synchronized with the AMD PI package. Remove items that do not apply to the Stoney APU, rewrite the comments associated with the PCIe devices, and fix up the SPD register association to match the 00670F00 chip.h. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e) Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17218 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16mb/intel/kblrvp: Increase preram cbmem console sizeNaresh G Solanki
Some part of preram cbmem console output is truncated. Increase preram cbmem console size to 0xd00 to avoid the same. Change-Id: Idbcbb3d1f433668a0e5375679f56fbe562d39ddd Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17840 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16drivers/i2c/generic: Allow mainboards to export reset and enable GPIOsFurquan Shaikh
Add power management type config option that allows mainboards to either: 1. Define a power resource that uses the reset and enable gpios to power on and off the device using _ON and _OFF methods, or 2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can directly toggle the GPIOs as required. GPIO type needs to be updated in drivers_i2c_generic_config to use acpi_gpio type so that it can be used for both the above cases. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that elan touchscreen works fine on reef using exported GPIOs. Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17797 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16google/eve: Enable touch devicesDuncan Laurie
Enable the actual touch devices to be probed by the kernel and remove the placeholder devices that I put in before and were used for initial bringup. BUG=chrome-os-partner:58666 TEST=tested on eve Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16google/eve: Enable native mode for UART pins in bootblockDuncan Laurie
Put the UART pins into native mode in bootblock so they are not floating when we try to communicate with H1 over I2C. Without a serial console enabled BIOS these pins were not configured until ramstage. BUG=chrome-os-partner:60935 TEST=Boot Eve board without serial console and H1 TPM enabled Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15mb/roda/rv11: Add new boards Lizard RV11 and RW11Dennis Wassenberg
The Roda Lizard RV11 is a comparatively lightweight, full-rugged notebook. It's based on a 17W TDP dual core Ivy Bridge CPU. The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o options). The RV11 is the first board to use the native graphics initialization by libgfxinit. Tested so far, are the internal eDP port, DP and VGA. Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-15mb/ga-945gcm-s2l: Fix resume from suspendArthur Heymans
Checking for memory self refresh can generate false positives, as explained in faa6beb: "northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option". This seems to be the case for this motherboard. TESTED on ga-945gcm-s2l. Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17617 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-15mainboard/google/reef: clear normal MRC cache on recovery retrainAaron Durbin
For Chrome OS the normal MRC cache should be cleared when a hardware retrain recovery request is observed. The reason is that since there are 2 different MRC cache slots there needs to be a mechanism which allows an end user make a system bootable again if the MRC settings happen to not allow the system to boot any longer. Therefore, one just needs to enter recovery with the hardware retrain flag and the system normal MRC cache slot will be invalidated. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17871 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15google/reef: Remove VARIANT_DIR definitionMartin Roth
VARIANT_DIR is defined in coreboot/Makefile.inc, so doesn't need to be defined in each mainboard. Change-Id: Ic93957b710e4a9863774de7fcf3bd006696b6aa1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17841 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-14google/eve: Configure I2C3 pins as GPIO inputsDuncan Laurie
On this board i2c3 bus is connected to the display TCON, but it is acting as the master when it has power so it can read from its own EEPROM on the bus. In order to prevent any possible issues in S0 make these pins input on the SOC. BUG=chrome-os-partner:58666 TEST=tested on eve board, but this bus was not used before so there is no visible change in behavior. Change-Id: Ide32f45ee33ca986fd3249a5161e01edf99d6e22 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17800 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13mainboard/google/reef: implement phase enforcement pinAaron Durbin
On upcoming boards an optional pull up is applied on GPIO_10 to indicate if the board should have security features locked down for a shipping system. Provide a weak pull down so that all boards will indicate a logic 0 until the stronger pull up resistor is stuffed. BUG=chrome-os-partner:59951 BRANCH=reef Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17803 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-13vendorcode/google/chromeos: Fill in firmware ID regionsPatrick Georgi
Chrome OS images have three firmware ID regions, to store version information for the read-only and the two read-write areas. Fill them with a suitable default and allow configuring a different scheme. There's already an override in google/foster and google/rotor to match the naming scheme used so far (in depthcharge). BUG=chromium:595715 BRANCH=none TEST=/build/$board/firmware/coreboot.rom has the expected values in the regions. Change-Id: I5fade5971135fa0347d6e13ec72909db83818959 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2e3be81faa8d21f92325294530714a4b18a1b3e Original-Change-Id: I2fa2d51eacd832db6864fb67b6481b4d27889f52 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/417320 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/17788 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-13lenovo: Don't use extern with functionsKyösti Mälkki
Change-Id: I8313ba1d93922297e5061701dad47d07617d1dcd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13mb/lenovo/*00: Remove Roda/RK9 specific codeNico Huber
Change-Id: Iacf2e1c0b8003a3588ccbf79e17500ed12f39503 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17786 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-12google/pyro: Set PL2 override to 15000mWKevin Chiu
This patch sets PL2 override value to 15W in RAPL registers and sets DPTF PL2 Max to 15W BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17779 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11nb/intel/i945: Make pci_mmio_size a devicetree parameterArthur Heymans
Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. A safe minimum of 768M is also defined since using anything less causes problems (if 4G of ram is used). Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16856 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-11intel/nehalem: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel/i945: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Scratchpad register was read too late in ramstage so acpi_is_wakeup_s3() did not evaluate correctly. This fixes low memory corruption at 0x1000-0x102c and the lack of coreboot tables (util/cbmem not working) after S3 resume. This also fixes console log from reporting early in ramstage "Normal boot" while on "S3 resume" path. Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel/gm45: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setupKyösti Mälkki
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With this change, CBMEM region is set early-on as WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09mainboard/google/reef: fill in NHLT ACPI OEM header fieldsAaron Durbin
Fill in the NHLT ACPI OEM header fields to differentiate different audio solutions on a per board basis. This handles boards that share a firmware that are differentiated by the SKU id and boards that have their own firmware. For the latter, the Oem Table ID uses the VARIANT_DIR to differentiate. "reef" is always used for Oem ID which is treated as more of family in this case. iasl -d shows the following on reef: [00Ah 0010 6] Oem ID : "reef" [010h 0016 8] Oem Table ID : "reef" [018h 0024 4] Oem Revision : 00000008 BUG=chrome-os-partner:60494 BRANCH=reef Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17772 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-09mainboard/google/reef: add board SKU'ing supportAaron Durbin
There are 2 gpios on reef-like boards that can be composed into a SKU. Add support for identifying the SKU value using the base 3 gpio logic. Also export the SKU information to the SMBIOS type 1 table. BUG=chrome-os-partner:59887,chrome-os-partner:60494 BRANCH=reef Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17771 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-08google/eve: Add ASL code to describe SPI FPC1020 controllerDuncan Laurie
There is ongoing work to link SPI bus and devices in to the devicetree so this can be generated, but for now put in the raw ASL code to describe this controller so it can be used by the factory. BUG=chrome-os-partner:55538 TEST=successfully load fpc1020 kernel module on eve board Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17776 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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