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2021-04-09mb/intel/adlrvp: Enable HECI1 communicationSridhar Siricilla
The patch enables HECI1 interface to allow OS applications to communicate with CSE. BUG=None TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0) Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-09mb/google/mancomb: Add Codec configrationEric Lai
Enable I2C2 in devicetree and fill ACPI information for Codec. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib75ef99cbca8b2f38268705704e7616b456f19d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Add Bluetooth configurationEric Lai
Configure the BT disable GPIO to logic low in order to enable Bluetooth. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7661dea682cbe0ae5e169d87e794ed6ed3c83b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Update GPIO configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie3917c10ecf37c914dbadce5949b8f4f772abd5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Enable AP <-> H1 communicationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I29be8572bc7bb366347eabe553be49775dec46a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Add initial I2C configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I483c2e77eedcb434709b67bf9b3fbca636499508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/dedede/var/boten: Configure Acoustic noise mitigation UPDsStanley Wu
Enable Acoustic noise mitigation for boten and set slew rate to 1/8 which is calibrated value for the board. BUG=b:180668001 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Change-Id: I75851bd7c279feeab4ab94f4c82d55bf0e5ce316 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-09drivers/tpm/Kconfig: Rename TPM_INIT to TPM_INIT_RAMSTAGEArthur Heymans
Rename the Kconfig parameter to more accurately reflect what it does. TPM can be initialised in a different stage too, for instance with VBOOT it is done in verstage. Change-Id: Ic0126b356e8430c04c7c9fd46d4e20022a648738 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-09mb/ocp/deltalake: Override DDR frequency limit via VPD variableTim Chu
Use VPD variable "fsp_dimm_freq" to select DDR frequency limit. Tested=On OCP Delta Lake, DDR frequency limit can be changed via VPD. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-04-09mb/{google/jecht,intel/wtm2}: Remove NOOP APM finalize callArthur Heymans
The intel/soc/broadwell smihandler has no handler for this APM call. Change-Id: I2bcec7cce00d433a197a9e2fb01434a2998e1452 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52167 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09mb/google/volteer/var/lindar: Configure unused GPIOs as NCKevin Chang
Configure unused GPIOs as NC BUG=b:180830117 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I0ba51dc262ccbf22b45d3be4b65e006f92587fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-09mb/google/asurada: early-init eMMCWenbin Mei
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, Depthcharge needs it 20ms after started) so we have to start initialization in coreboot. On Hayato Chromebook this can save ~100ms in total. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51973 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09mb/google/asurada: select mmc storage configWenbin Mei
Select mmc storage config for asurada. Build MTK host mmc driver. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-08mb/amd/bilby: Enable postcode on port 0x80Ritul Guru
selecting SOC_AMD_COMMON_BLOCK_USE_ESPI will disable the lpc decodes, so not selecting that keeps the lpc decodes. Change-Id: I03a8d4b804cee205b9e06b00e2e5a442452f8f86 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52016 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/amd/bilby: enable boot from NVMe SSDRitul Guru
These changes involve NVMe specific GPIO programming to enable pcie NVMe SSD boot. Add nvme dev,func in devicetree and also remove unused GPIOs programmed in Bilby. Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51674 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boardsFelix Held
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the corresponding SCI mapping register, but didn't set up the SCI level and trigger type, so that couldn't have worked on most of the boards. The only boards where I think this was actually tested are the google/zork ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is GPIO mode instead of the WAKE_L mode, but at least the SCI was configured correctly. The new PAD_NF_SCI macro can configure both the right GPIO mux setting and set up the SCI configuration correctly, so use this new macro for the GPIO_2 pin. For test purposes I also added the corresponding GPIO_2 configuration to amd/mandolin to see if the affected registers end up having the expected value using the HDT debugger to look at the registers, but didn't test the wake-up functionality, since S3 resume isn't working on amd/mandolin yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGSFrans Hendriks
The CACHE_MRC_SETTINGS option is already selected in SoC Kconfig. BUG = N/A TEST = Build and boot facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: I1c7fd5ec36726724939660bf506a45a44848f8c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-08mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMPFrank Wu
Update the ACPI name from AMDP1015 to 1002105 based on b/177971830#180. AMDI1015 -> AMD platform with RT1015 10021015 -> AMD platform with RT1015p Reference: https://www.spinics.net/lists/alsa-devel/msg124694.html BUG=b:177971830 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52127 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: Unmask eSPI keyboard IRQRaul E Rangel
PS/2 keyboard used IRQ 1. BUG=none TEST=Boot guybrush and see internal keyboard working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I97b7382eac28aae2cc82f430c58cf8066b9701e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52143 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: Remove PS/2 mouse configRaul E Rangel
Guybrush doesn't have a PS/2 mouse. BUG=none TEST=boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I87e51d23b69cfd6ad7bb88b364714d679e92728f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52145 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/google/guybrush: PCIe GPIOs - enable enables, disable resetsMartin Roth
To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WWAN & WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/52115 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd`Angel Pons
This option's value is not used anywhere. Remove it. Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-08soc/intel/skylake: Drop unnecessary `ignore_vtd` optionAngel Pons
It is zero for all mainboards. If one really wanted to ignore VT-d support, a user-visible Kconfig option would be a better approach. Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-08mb/google/brya: Change GPP_D15/D16 default to lowEric Lai
WFC Camera driver will control the power sequence. Therefore, set default to low. BUG=b:184024459 TEST=abuilds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-08mb/google/dedede/var/metaknight: Add support to handle pen detectionDavid Wu
Update devicetree and gpio setting of metaknight to handle pen detection. BUG=b:180426949 TEST=Build and check behavior is expected. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ieeca20eff57b16217a13d996dca3f662911f3e5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-07mb/google/guybrush/port_descriptors: add dummy descriptorsFelix Held
This is a temporary workaround for a bug that breaks graphics due to some power management issue. Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52141 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptorsMartin Roth
pcie_rst isn't working correctly, so use the AUX resets to reset the PCIe devices before training. BUG=b:182202136 TEST=See PCIe devices train & enumerate Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07mb/amd/majolica: add DXIO and DDI descriptorsFelix Held
TEST=Worked on Matt's Majolica board. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51956 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07mb/amd/majolica: add PCIe devices to devicetreeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I838aeda2e6c403eaa3388a6b934e7ab6b4e918e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/guybrush: add DXIO and DDI descriptorsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSPMatt Papageorge
This patch adds the functionality to write the DXIO and DDI descriptors to the UPD data structure to the SoC code and adds the mainboard_get_dxio_ddi_descriptors function to each mainboard using the Cezanne SoC that gets called to get the descriptors from the board code. Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07mb/google/mancomb: Enable USB ports in devicetreeEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-07mb/google/mancomb: Enable PCIe devices in devicetreeEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Add initial fch irq routingEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/52117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Add eSPI GPIO back to init tableEric Lai
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Configure UART0 gpio in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Enable DISABLE_SPI_FLASH_ROM_SHARINGEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1d28c2335b095a77285dcb261a0dffe96d129c46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/google/mancomb: Enable early EC Software SyncEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-07mb/sapphire/pureplatinum/cmos.default: Remove `volume` entryNicola Corna
Following commit de50d39, remove the `volume` entry from cmos.default. Change-Id: Ieebafffa0d2fbf6cdd24cff4ddefe090a727cbfa Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-06intel/tigerlake: Add Acoustic featuresShaunak Saha
On VCCin there was an oscillation which occurred just as the kernel started (kernel starting... message). On some devices, this behavior seems even worse. In previous platforms VCCin toggled for a few ms and then was stable. For volteer, this happens at the same point in time for around 40ms. However, it starts oscillating again later in the boot sequence. Once at the root shell, it seems to oscillate indefinitely at around 100-200Hz (very variable though). To fix this we need to control the deep C-state voltage slew rate.We have options for controlling the deep C-state voltage slew rate through FSP UPDs. This patch expose the following FSP UPD interface into coreboot: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8. TGL has a single VR domain(Vccin). Hence, the chip config is updated to allow mainboards to set a single value instead of an array and FSP UPDs are accordingly set. BUG=b:153015585 BRANCH=firmware-volteer-13672.B TEST= Measure the change in noise level by changing the UPD values. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06Revert "mb/google/guybrush: Disable GFX"Raul Rangel
This reverts commit 52e61945588bc327844acc4658426861d63ad189. Reason for revert: Graphics actually works now. I should have abandoned this CL. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I83aac3a2c616bb434706f23e36549760bc764080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-06mb/facebook/monolith: Allow TPM initializationWim Vervoorn
TPM_INIT is disabled by default. This prevents TPM to be operational when VBOOT is disabled. Remove the TPM_INIT disable. BUG=N/A TEST=tested on facebook monolith with VBOOT disabled. Change-Id: I84d525a18c84643903922fef0a11dcf98abbbe4d Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-06mb/facebook/monolith: Update VBOOT settingsWim Vervoorn
Make sure the standard for the board options are set when VBOOT is enabled. BUG=N/A TEST=tested on facebook monolith Change-Id: I9749eeeffbd26e7c5caaeb7c0407a765cf093337 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-06mb/google/volteer/var/lindar: Increase Goodix touchscreen reset delay to 180 msKevin Chang
1. Follow GT7375P Programming Guide_Rev.0.6 to increase reset delay to 180ms. BUG=b:181711141 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I82222ca094eead7e9e691857e128243cfe7c310e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-06Lindar/Lillipup: Enable Bayhub SD card reader power-saving modeKevin Chang
Enable Bayhub SD card reader power-saving mode for Lindar and Lillipup. BUG=b:173676531 TEST=Boot to OS and test with SD card function. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-06mb/intel/adlrvp: Update iDisp Link UPD settingsFrancois Toguo
This changes updates the iDisp-Link T-mode to 8T required for ADL-M. The update is made because the HW on ADL now supports 8T mode. BUG=None TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/intel/adlrvp: Enable Camera in ADL-M RVPVarshit Pandya
1. Configure Power Enable, Reset and Clock GPIO for both camera 2. Use same ASL code as ADL-P RVP Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC TEST=Build, Boot and Verify streaming in both Camera Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06mb/google/kukui: Add flag for MIPI_DSI_MODE_LINE_END ANX7625Jitao Shi
Config ANX7625 line data end same time on all line. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: Ia1dc217138a98a79ef2f31225b52ba2b1aaf8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-06mb/asus/p2b: Add option table supportKeith Hui
Just do it already. The two SCSI-specific options for p2b-{ls,ds} will be wired up in a followup. They will be ignored by boards without the hardware. Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06mb/google/guybrush: Disable GFXRaul E Rangel
This is locking up the OS. For now this will unblock booting. BUG=b:183971103 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-30 15:13:44 +0000